Table of Contents
Advertisement
2.1
DESCRIPTION
The
Communications
System
Analyzer can perform
nine basic
functions:
it
can act
as a generator,
a
watt-
meter,
a
monitor,
a duplex generator,
a code
synt
he-
sizer,
a
frequency
counter,
a
digital
voltmeter (DVM),
an
oscilloscope,
and
a
distortion/SINAD
meter.
Mea-
surements
can
be
printed
out
via
the
Printer
Port.
General
operation of
the
unit will
simultaneously
incorporate
all
these functions.
The
following
discussion will
cover the
block
dia-
grams
for each of the basic
functions plus a
discussion
on
the
processor
control of the
system.
A functional
block diagram
of
the total
system is shown
at the
end
of the
section
in Figure
2-1.
To
clarify
the
total
system
configuration,
only the major
signal
paths
between
each
of the
modules are
shown.
2-2
SYSTEM
CONTROL
2.2.1 PROCESSOR
System control is
t
he primary responsibility
of the
internal
microprocessor.
T
o
control
the
operating
mode,
the
processor
manipulates inputs
from
front-
panel
controls and
system-status inputs.
From the
front
panel,
the
processor monitors the
keyboards,
the
function-select
switch, the
modulation-control switch,
the RF
-scan switch,
the image
switch,
the
bandwidth
switch,
the
horizontal
and vertical
range switches,
and
the
step-attenuator
switch.
This information,
plus
internal
status
information,
causes
the
processor
to
display the
appropriate
information
on the
CRT,
to
program
the
center
frequency, to
set
up the
generate
or
monitor mode, and
to
make
the internal switching
·
arrangements
for
the
selected operating
state.
2-1
SECTION
2.
SYSTEM THEORY OF OPERATION
2.2.2
PROCESSOR BUS
The
interface
to and from the microprocessor
is
via
the
processor
bus.
This
bus
consists of a 16-bit address
bus,
an 8-bit data
bus,
and
a 7 -bit control
bus.
The bus
interfaces the
processor
to
its
program memory
(ROM),
scratch
pad memory
(RAM),
IEEE
interface
opt
ion,
cellular
mobile
telepho ne option, RS-232
option,
Trunking
option,
Secure options,
and
the
peripheral-interface adapters
(PIA).
The
PIA
is
the
mechanism
by
which
the
processor
interfaces with the
system.
A
PIA
consists of
a
dual
S-bit
latch
which
may
be
programmed
as either
an input
or
an
output
for the
microprocessor.
System input and
control
informa-
tion passes to
and from the microprocessor
via t hree
system control
busses
attached
to
a
PIA,
which
is
located
on the Processor Interface board (All).
2.2.3
CONTROL BUSSES
T he three control
busses within
t he
System
Ana-
lyzer
are
called the
RF
control
bus and AF
control
busses
1
and
2. The
AF control
busses
consist
of a
4-bit address
bus, a 4-bit
data
bus, and
two enable
.
lines.
The
four
address
bits
determine
which of
16
possible
latches the four
bits of
data are
to
be
sent to
or
received
from.
The
enable
lines t
rigger
the actual
t
ransfer of
data. The
RF control
bus is a clocked
serial
bus
which
consists of five data lines, a
clock
line,
and
a
latch
line. The
serial
data
stream
is
24
bits
long.
T
ables 2-1
through
2-6
show the
busses
and
the
func-
tion of eacl:
bit.
Figure
2-2 at the
end
of t he section
shows
the
overall bus
structure of
the System
Ana-
lyzer.
Advertisement
Table of Contents
Troubleshooting
