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SECTION
13.
PROCESSOR INTERFACE BOARD (A11)
13.1 DESCRIPTION
The Processor Interface board
contains
the
digital
voltmeter
(DVM), frequency counter, system t
imer,
and
t he
processor
interface
for
the
two
system control
busses:
audio
frequency
(AF
bus)
and radio
frequency
(RF
bus).
The DVM
can
measure both
de
and ac
rms
(root-mean-square) voltages.
The
frequency
counter
uses
two different
measuring techniques: t
he
direct
count
and
the
reciprocal
count.
A
block diagram
of
the
Processor
Interface
board
is
shown
at the end of this section
in
Figure
13-1,
a
sche-
matic
in
Figure
13-2, and
t
he printed
wiring
board
assembly
and
parts
list in
Figure 13-3.
13.2
THEORY OF OPERATION
13.2.1
SYSTEM CONTROL-BUS INTERFACE
13.2.1.1 General
In
terface
between
the processor
busses
and
the
sys-
tem
i~
through
peripheral-interface adapters
(PIA)
.
The
P IA
is a
single
integrated-circuit chip that pro-
vides
16 input/output
latches
(PAO-PA 7 and PBO-
PB7)
which
can either
be
read
from
or written
into by
the
processor. The
PIA
also
contains
four control
lines:
two
oft
he~e,
CAl and
CBl, act
as
input-only lines
for
processor
interrupts,
and
the
other two, CA2
and
CB2,
act as
output-only
control
lines.
The two system con
-
trol
bu
s~es
(AF
and
RF) use a
single P IA
(U1)
.
13.2.1 .2
AF Control
Bus
The AF
control bus
consists
of eight
lines
split
into
four
data
lines (PBO-PB3)
and four address
lines
(PB4-
PB7)
.
The
address
lines
define
the
particular
latch in
which
the data is to
be
stored,
or
the
buffer from which
data
is
to be
obtained.
One additional
address line,
the
bus-enable
line,
is
required to enable
the
address-
decoding circuitry.
The AF
control
bus has
two bus-
enable lines,
AF BUS EN 1 and AF BUS EN
2,
which
provide a total
control-bus capability
of 128
bits.
The
AF
BUS
EN
2 line
enables the address-decoder
cir-
cuitry
on
the Front-
Panel
Interface
board
(Al5)
and
t
he
P rocessor Interface
board
(All).
The AF
BUS
EN
1
line,
which
comes
from the
Processor board
(A14),
enables
the
address-decoder
circuitry
on
the
Scope/DVM Control
board
(A
7)
and the
Audio
Syn-
thesizer board
(A 10).
13-1
13.2.1.3
RF
Control
Bus
The
RF
control
bus
is
a
clocked serial bus which
consists of five
data lines
(PAl, PA3-PA6),
a
data
clock
line
(CA2),
and
a
latch
line
(PA7).
The
data
stream
is
24
bits
long. Four
of these
data
lines
(OFFSET
DATA,
310-440
DAT A, 24 DATA,
and
60.5 DATA)
program
the
phase-locked-loop
(PLL)
ICs
on
the
Duplex
Gen-
erator
and
the RF
Synthesizer. These
ICs
disregard
the
first
5
bits
of
the
serial
data
stream
and latch-in the
last 19 bits.
The
other
data
line,
PA6 system
control,
controls
t he
Receiver board
(A8)
and
RF
Synthesizer
board
(A9). The
RF Synthesizer
is
programmed
by
the
first 8
bits of
the
system-control
data
line,
and
the
Receiver
by
the
last
16
bits.
13.2.1.4
Timer
The timer
(U35)
provides interval
timing
to
the
processor
for tone encoding and decoding
and other
functions.
In
the
encode interval-timing mode,
the
processor
programs the
desired
interval
and
initiates
the timer
with
control words on the
data
lines
and an
enable
pulse
on
the
Eline. The
timer will interrupt
the
processor
when
the
programmed
interval
is com-
pleted.
In
the decode interval-timing mode,
the
pro-
cessor
will
start
and
stop t he
timer. The
processor
will
then
read
the
interval
time from the
timer.
The
timer
reference frequency
is
the
SYNTH
1
KHz, a
1-kHz
square
wave locked to the
system's refe rence fre-
quency.
13.2.2
DIGITAL VOLTMETER (DVM)
13.2.2.1
General
The DVM
measures
either
the nine
internal
voltage
points
or
the
external
voltages.
The levels of
the
inputs
to
t he
DVM
are
auto-ranged for
3-digit
accuracy.
The
DVM consists of
an
analog-to-digital
(A/D) converter,
a root-mean-square
(rms) converter,
and
t he
DVM/
FREQ
COUNTER
PIA
which
provides the interface
between the
DVM and
the
processor.
13.2.2.2
A/D
Converter
The
AID
converter
(U29) converts
positive
de volt-
ages.
between
0
and
1023 m V into
a 10-
bit
digital
word.
For negative
voltages,
the
signal is
conver ted
to a
pos-
itive
voltage by the
rms
converter (U27), with the
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