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17.2.4
ENHANCED DUPLEX GENERATOR
BOARD
(A
17 A3) (required for 900 MHz
Trunking Option)
17.2.4.1 Temperature Compensated
Crystal
Oscillator
(TCXO)
The Enhanced Duplex Generator uses
a
TCXO to
obtain
the tighter frequency tolerance required by
some
trunking
radio
bands.
Several frequencies are generated from the TCXO
by dividing the
frequency of the output.
Signals at 6
MHz and
10
MHz are obtained
by
dividing
by
5 and
3
respectively. A
5
MHz signal is
generated
by
dividing
the 10 MHz
signal
by
2.
17.2.4.2 General
The Enhanced Duplex Generator
provides
an RF
output whose frequency is
offset
from the receiver's
center
frequency by either fixed 45 Mhz,
39
MHz,
or
55
MHz, or an adjustable offset of 0 to 10
MHz
in
5
kHz
steps.
The 45 MHz offset is obtained by mixing the local-
oscillator signal from the Wideband Amplifier (LO
OFFSET), which is offset by
10.7
MHz from the
desired receiver
signal,
with a 34.3 MHz signal gener-
ated by a phase-locked
loop
(PLL).
The
39
MHz offset is obtained by mixing the 6 MHz
signal with the 34.3 MHz PLL to generate a
28.3
a MHz
signal.
This is then mixed with the LO
OFFSET
sig-
nal.
The
55
MHz offset is obtained by mixing the 10
MHz
signal
with the
34.3
MHz PLL to generate a 44.3
MHz
signal.
This
signal
is then mixed with the LO
OFFSET
signal.
The 0 to 10
MHz
adjustable offset is obtained by
mixing the LO OFFSET signal with a 0.7 to 10.7 MHz
signal.
This
signal
is
generated by mixing the
34.3
MHz
PLL with a
35
to 45 MHz PLL.
A block diagram
of
the Enhanced Duplex Generator
board is shown
at
the
end
of the
section
in Figure
17-
10, a
schematic
in Figure 17-11, and the printed wiring
board
assembly
and parts list in Figure 17-12.
17.2.4.3
Phase-Locked-Loop (PLL)
Control
Each
phase-locked-loop on
the Enhanced Duplex
Generator board
uses
a PLL integrated
circuit
(IC).
This IC provides digital dividers, control functions, the
phase detector, and a reference-frequency
oscillator.
The reference oscillator
is
divided-down by the refer-
ence
divider
to set
the reference frequency
of
the PLL.
This
signal
is applied
to
the phase detector, where it is
compared
to
the output
of
the
divider chain
(divide-
by-N
and
divide-by-A).
The
selection of the
dividers
(reference,
divide-by-N, and divide-by-A)
can
be pro-
17-5
grammed
by using
serial
data lines. Each
serial-data-
programmable
IC
provides
two
latched open-drain
outputs that can be used for external switching.
17.2.4.4 PLLs
17.2.4.4.1
General
The
35 to 45
MHz PLL
consists of a
PLL
IC,
a loop
filter, a voltage controlled
oscillator (VCO), an
ampli-
fier, and a
dual
modulus pre-scaler.
The PLL IC
(U2)
divides the
5
MHz
signal
by 1000
to
obtain
an internal
5
kHz reference. The feedback
signal
is
obtained
from the
divide-by-32/33
dual
mod-
ulus pre-scaler
(U4).
17.2.4.4.2
Loop Filter
Loop filter U6 sets the bandwidth and
stability
of the
loop and attenuates the reference-frequency
compo-
nents coming from the phase detector. The
3-dB
bandwidth of the
35
to 45-MHz
loop
is
22Hz.
The
loop
filter incorporates a lead-lag network (R29, R30, and
C38)
to reduce the resistor values of R21-R25. This
allows for a
faster loop-lock
time. Diodes
CR7
and CR8
help the operational amplifier
(U6)
slew
t he
large-value
capacitor
(C38).
The output of the
loop
filter tunes the
VCO frequency to the value needed to maintain
phase
lock.
17.2.4.4.3
VCO and Amplifier
The
35
to
45-MHz
VCO (Q3 and Q4)
is
a series-
tuned oscillator that resonates
varactor
diodes
CR5
and
CR6
with the
inductance
in
the
24
turns of trans-
former Tl. Transistor Q10 is the VCO ON/OFF
switch
which
is
controlled by the PLL
IC
(Ul)
via
the SW1
output.
The amplifier
(QS)
following the VCO pro-
vides an
output
of
+
7
dBm.
This
signal
is
attenuated
by R39 and R40 before
going
to the two-modulus
pres-
caler, U4.
17.2.4.5 34.5
MHz PLL
17.2.4.5.1 General
The
34.3
MHz PLL has
the
same elements as the
35
to 45 MHz
PLL.
The
PLL IC
(U1)
divides
the
10 MHz
signal
by 1000
to obtain an
internal reference
of
10 kHz. This PLL
also
uses
a divide-by-32/33
dual modulus pre-scaler in
the
feedback path.
17.2.4.5.2 Loop Filter
Loop filter
US sets the
bandwidth and
stability of the
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