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polarity
information
detected by
t
he
SIGN
DETEC-
TOR (U34). The information bit for the sign detector
is
latched
into the
DVM/counter buffer
(U20).
The
processor initiates an
AID
conversion with a
pulse
on
the
start line
(U29 PIN21). The
AID
converter
signals
the processor that the conversion is complete by a
pulse
on
the
end
line
(U29
PIN23).
The processor,
in
turn,
enables
the
output
drivers on
the
AID,
sets
the
DVM/
COUNTER buffer
to the DVM mode,
and
inputs the
10-bit
word from the
AID
and
the
sign
bit.
13.2.2.3
Internal DVM
Internal
DVM
voltages
in
the
System Analyzer are
all
positive
and proportional to
certain
parameters
in
the system. (See
Section
9, Scope/
DVM Control
board
A
7,
paragraph
9.2.8.2.)
These signals
are auto-ranged
over two decades to a 0 to 1-V de
range
on the A 7
board
and
routed
to the INT DVM TO
AID
input
on the All
board.
The processor makes
an internal measurement
by
selecting
the internal
path
which routes
the
signal
directly
to
the
AI
D
converter
for conversion, as
described
in paragraph
13.2.2.2.
13.2.2.4 External DVM
13.2.2.4.
1 General
In
the external
DVM
mode,
voltages applied to the
input jack on the front
panel
are auto-ranged on the
Front-Panel
Interface
board (A15)
to provide four
full-
scale displays
of
1,
10, 100,
and 300V.
From
A15, the
signal
is passed
directly
through the A
7
board
to the
EXT DVM TO
AID
input
on
the
All
board.
The
resulting
dynamic
voltage
range
at the
EXT DVM TO
AID
input is 0 to 1 Vrms.
This
signal is
amplified
at
U28
by
a
voltage
gain
of 3.5
and applied to
the
rms-to-
dc converter.
The
resulting output is
applied
to atten-
uator R22 with a voltage gain
of 1/3.5.
The amplifier
and attenuator allow the rms-to-dc
converter
to work
with
larger
signal
levels. This provides
a
net
increase
in
conversion
speed.
The
output
of
the attenuator
is
then routed to the
AID
converter
for conversion, as
described in
paragraph
13.2.2.2.
13.2.2.4.2
OC/AC Mode
In
the de
mode, inputs
are
low-pass
filtered in the
A15 board
before entering
the
All board.
The
rms-to-
dc
converter
reads true rms; therefore,
the
output
for
a
de
input
is
the positive
square
root
of
the
input
square
-
that
is,
the absolute value
of
the input
volt-
age.
The polarity
of
the
signal
is
determined by the
sign
detector,
U34.
In
the
ac
mode, inputs are capacitor-
coupled in the A15 board. Therefore,
only
the
rms
voltage of
the ac
compo:1ent is
measured.
13-2
13.2.2.5
Distortion Reading
In
the distortion-measurement
mode, the 1-kHz
fundamental of the input
is
filtered out
by
a
notch
fil-
ter on the
A
7
board. The
distortion
products are
routed
to the
EXT
DVM
TO
AID
input
of the
All board
for
input
to t
he
processor
by the
AID
converter.
The input
to the notch filter is
rectified
and averaged on the A
7
board
and
then routed through
the
internal
DVM
cir-
cuitry for
measurement.
To
obtain
the
percent
of dis-
tortion
for a 1-kHz input
signal,
the
processor
divides
the
rms
output
voltage of the notch filter by the
aver-
age
rectified
input voltage to
the notch
filter.
13.2.3
FREQUENCY COUNTER
13.2.3.1
General
The frequency
counter
uses
two
methods to
deter-
mine
frequency:
direct
counting
and reciprocal
count-
ing.
In this manual the
direct method
will
be
called
"frequency
counter"
and
the
reciprocal
method will be
called
"
period counter."
In
the direct
method,
the counter
counts
cycles
of the
unknown
signal
for a
precisely
known
length
of time,
called
a
gate
time.
The
resolution
of
the
measured
sig-
nal
is directly
proportional
to
the
gate
time,
one
Hertz
in one
second. The reciprocal method
measures
fre-
quency by
counting
the
number
of
internal
clock cycles
per
one
period of
the unknown
signal.
This
technique
makes the
resolution
of the
measured
frequency pro-
portional to the frequency of the internal clock. For a
1-MHz
internal clock, the measurement of
a
1-kHz
signal
would take 1
msec
and provide a
resolution
of
1Hz.
Three
possible
signal sources
are available to the
frequency counter for frequency
determination.
The
desired
signal
is selected
and sent
to
the
counter
by
select
switch
U8.
For
external
inputs,
t
he
EXTER-
NAL
COUNTER
lines
from the
Front-Panel
Inter-
face
board
(A15)
provide
the input which
is buffered
by
U3B,
Q4
and
Q5 on the All board.
The
signal
for
off-the-air tone-sequence decode is DEMOD CAL
AUDIO,
which is routed through
the
A7
board
to
the
INT
SCOPE
TO RNG
SW
line.
This
signal
is
con-
nected
to
Al5, where it
is
routed
through
the range
switch
to
the
EXTERNAL COUNTER
input.
Moni-
tor
frequency
error
is
determined
from
the
IF
/BFO
FREQ line
by comparing
that frequency
to 700kHz.
13.2.3.2
Frequency Counter
The frequency
counter consists of a gate-time
gen-
erator
(U9-U13),
an accumubtor
(Ul8,
U19)
,
a buffer
(DVM/COUNTER
BUFFER
U20-U22),
a P
IA
(U2, as
described in paragraph
13.2.1.1),
and control
circuitry
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