Table of Contents
Advertisement
14.4.2.3 Random Access Memory (RAM)
The random
access
memory provides
temporary
data
storage
for the processor and
for the CRT
alpha-
numeric display. RAM is partitioned into
unpaged,
processor paged, and
option
paged RAM. The
unpaged
RAM can
store 2048 8-bit
words,
of
which 512 are used
for
the
CRT
display
data.
The unpaged RAM is located
from
000 to 7FF
hex. Each paged RAM
can store 2048
8-bit words
and is located
from 800 to
FFF hex. The
processor paged RAM
is enabled
by pulling
output
PB4
of U38
low. Pulling
this
output high
causes
XRAM to
go
low
when
a
valid address
occurs, ena-
bling
option
paged RAM. To prevent more
than one
option
RAM from being
enabled, each
option has
another enable line
that
must be
set.
14.4.2.4 Nonvolatile Memory (NVM)
The nonvolatile memory provides
storage for 2048
8-bit words.
Data
that is to
be
held during
power-off
is
held in
the NVM,
which
consists of a
battery-backed
RAM.
When the power is turned
on, the
microproces-
sor
reads
the NVM contents to obtain
its
start-up
mode, the RF
and
tone-memory presets, and the
remainder
of
the preset data. If the
operator changes
a
preset,
the microprocessor
changes
the
data
in
the
NVM to
reflect
the
new
preset.
14.4.3 INPUT/OUTPUT
Peripheral Interface Adapters provide input and
output latches for external
data to and
from the
pro-
cessor.
One
of the
PIAs
on this
board
(U39)
provides
for nine inputs from
the keyboard: five
row inputs
(ROW 0-4), and four column
inputs
(COL
0-3).
OPT
A DET
and
OPT B DET are
outputs
which enable the
program memory
for the
A and B
slot,
respectively.
Another input
(OPTO
DIR) provides
the
processor
with the optical encoder's
direction
of rotation.
14.4.4
CHARACTER DISPLAY
14.4.4.1 General
Characters are
displayed
on the CRT as
8 X
8 dot
matrices. One character
line
is composed of 32
dot
matrices, of
which
the
last
two
are
always
blank. A
dis-
play
frame is
composed of 16 character lines, of which
the
last
one
is
always blank. Thus, the
total
number
of
matrices
available
for
character display is 30
X
15 or
450. The two blank matrices and
the
blank
line
are
used
for horizontal and vertical
retrace
blanking,
respectively.
The display
is
generated
by dot
rows.
As
the CRT
sweeps
the first
dot
row of a character
line,
the character generator outputs a serial-bit pattern of
1s
and Os that turns the
CRT
intensity on and off. The
14-4
result is a
row
of
dots,
which combined
with
the
next
seven
rows,
forms a character.
The
frame
display
is
stored
at U26,
in
32X16 bytes
of
RAM. This
RAM
is
shared
by
the
character
gener-
ator and the
processor.
The two are
synchronized
to
access
the
RAM
during
alternate half
cycles
of
the
master E
clock. The
RAM multiplexer
(U28-U30)
allows
both
the processor and the character generator
to
have non-interference
access to the
RAM
every
other 0.5
microsecond.
In
RAM, the processor
stores
an
8-bit
word
representing
the character to be
dis-
played.
14.4.4.2
Timing Generator
The
timing
generator provides timing
signals
for
the
character generator. All the
timing
signals
are syn-
chronized
to the 1-MHz E clock from the micropro-
cessor.
The E and
Q
clocks are exclusive-OR'd to
provide
a 2-MHz
signal
which is used to clock the 8-
bit shift register
(U1). This clock signal provides
t
he
dot
rate.
The
1-MHz E clock is divided-by-four by U10,
and
the
resulting
signal
is used
to latch
one
dot
-matrix
row into
U3. This
provides
a dot-matrix
rate
of 250
kHz.
The divided-by-four
signal
is
further
divided
by
a
12-bit binary
counter
(U24
and U25), to
provide
a
row
rate of 7812.5
Hz, a
character
line
rate
of 976.5
Hz,
and
a frame
rate
of 61.04
Hz.
14.4.4.3 Character Generator
The character generator
simultaneously
scans the
RAM
in sequence with the CRT display scan. The
sig-
nals
for the CRT display scan come from the horizon-
tal
and
vertical character-sweep generators on the
Scope
Amplifier
board (A7). The
12-bit
binary
counter
provides the
9
bits
of
information stored in
RAM. As
each
location in RAM
is
addressed,
the
8-bit word
stored at
the
location is
latched
into
the
8-bit latch
(U3) at the dot-matrix rate
of 250
kHz. Seven
of the
bits are
held
in the
latch
and are applied to the
char-
acter
ROM
(U2);
the
remaining bit is not
used.
An
additional 3 bits from
the
12-bit
binary
counter tells
which
row
of
dots
is being
scanned.
Thus, the
10 bits
being
applied
to the
character
ROM define a particu-
lar dot row of a
particular character.
The 8-bit pattern
that
defines
this dot row is then available at
the
out-
put
of
the character
ROM. This
output
is
parallel-
loaded into
the 8-bit
shift register, Ul.
The
8 bits are
serially shifted out on
the
CHAR GEN Z-AXIS line
at
a
dot rate
of 2 MHz. The 12-bit binary
counter
also
provides
synchronizing signals
for
t
he
character-sweep
generators on the A
7
board.
The horizontal and verti-
cal
character-sweep generators
are
reset
and
started
by
one-shots
(U22A and
U22B
respectively). The hori-
zontal
one-shot
enable
is located
at
the
end
of
a dot
row.
The vertical one-shot enable has
two sources:
the
CHAR
GEN RESET line for dual-display mode, and
Advertisement
Table of Contents
Troubleshooting
