Epson Power Supply IC S1F70000 Technical Manual page 102

Note 1 : Precautions on Load Connection
When a load is connected between GND in the first stage (or potential below GND in the second stage
other than that) and V
When a normal output is not available at the V
off V , current may flows from GND in the first stage (or potential below GND in the second stage
REG
other than that) to the V
absolute maximum rating below GND in the second stage may be generated at the V
result, the IC may not work normally. For series connection, connect the diode D1 between V
V in the second stage as shown in Figure 8.4, so that no potential below GND in the second stage is
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added to the V
REG
Note 2 : Figure 8.4 shows 3 times step-up in the first stage and 4 times step-up in the next stage, but 4 times step-
up is possible both in the first stage and in the next stage unless the input voltage V
the specification value (6.0V). This means that each IC in this series connection is requested t satisfy the
specification values (V
V
O
V
DD
G
ND
Figure 8.5 Power Supply System in Series Connection
Note 3 : 2 times step-up in the first stage allows using the CAP- output in the first stage as the next stage clock,
but 3 times step-up does not. Attach an external R
Also, since the next stage external clock can operate according the CAP- output in the previous stage as
shown in Table 4.1 only when the temperature gradient C
same way when other temperature gradients are necessary.
Note 4 : In case of series connection, the voltage V
stabilization circuit operates, has temperature gradient. This means that V
rate as temperature changes:
V
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= C
T
T
S1F70000 Series
Technical Manual
in the second stage as shown in Figure 8.4, pay attention to the following.
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pin in the second stage through the load and a voltage higher than the
REG
pin.
-GND 6, 0V, V
DD O
First stage Next stage
Max. 6.0V
DD
(V ' (25˚C) – GND')
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EPSON
pin at the starting time or when the P
REG
-GND 24V). (See Figure 8.5.)
V '
O
V '
DD
G '
ND
as the next stage clock for internal oscillation.
OSC
is -0.6%/˚C, use the internal oscillator in the
T
-V (V '-V ' in Figure 8.5) of the IC, for which the
REG REG DD
S1F76640 Series
signal turns
OFF
pin. As a
REG
and
DD
'-GND' exceeds
DD
V '
REG
changes at the following
REG
2–59