Sharp UX-510A Service Manual page 56

UX-510ATH
FO-1470TH
SCE114 (IC9) Terminal descriptions
Pin
Pin List
No.
127 GPO[27]/BUSY
128 GPO[28]/PERROR
129 GPO[29]/SLCTOUT
130 GPO[30]/FAULTN
131 GPIO[29]/PIOD[0]
132 GPIO[30]/PIOD[1]
133 GPIO[31]/PIOD[2]
134 GPIO[32]/PIOD[3]
135 GPIO[33]/PIOD[4]
136 GPIO[34]/PIOD[5]
137 GPIO[35]/PIOD[6]
138 GPIO[36]/PIOD[7]
139 VDD
140 GPIO[0]/SR4IN
141 GPO[31]/SR3OUT
142 GPIO[37]/IRQ15n
143 IARESET
144 IACLK/DSPCSn
145 IA1CLK
146 SR3IN/DSPIRGn
147 SR4OUT
148 SR1IO
149 SA1CLK
150 VSSPLL
151 TSTCLK
152 DEBUGn
153 RDn
154 WRn
155 SYNC/GPO[20]
156 ROMCSn
157 CS1n/GPO[21]
158 VSS
159 SXIN
160 SXOUT
161 VDD
162 PM[3]/GPO[3]
163 PM[2]/GPO[2]
164 PM[1]/GPO[1]
165 PM[0]/GPO[0]
166 SM[3]/GPO[7]
167 SM[2]/GPO[6]
168 SM[1]/GPO[5]
169 SM[0]/GPO[4]
170 REGDMA/GPO[18]/CLKConfig[0]
171 WAITn/GPO[19]/CLKConfig[1]
172 VDDPLL
173 D[7]
174 D[6]
175 D[5]
176 D[4]
Input Output
I/O
Type Type
−
O 13Xs GPO[27] or P1284 returned status to host.
−
O 13Xs GPO[28] or P1284 returned status to host.
−
O 13Xs GPO[29] or P1284 returned status to host.
−
O 13Xs GPO[30] or P1284 returned status to host.
I/O Hu 13Xs GPO[29] or P1284 data or address driven by asic or host
(mode dependent).
I/O Hu 13Xs GPO[30] or P1284 data or address driven by asic or host
(mode dependent).
I/O Hu 13Xs GPO[31] or P1284 data or address driven by asic or host
(mode dependent).
I/O Hu 13Xs GPO[32] or P1284 data or address driven by asic or host
(mode dependent).
I/O Hu 13Xs GPO[33] or P1284 data or address driven by asic or host
(mode dependent).
I/O Hu 13Xs GPO[34] or P1284 data or address driven by asic or host
(mode dependent).
I/O Hu 13Xs GPO[35] or P1284 data or address driven by asic or host
(mode dependent).
I/O Hu 13Xs GPO[36] or P1284 data or address driven by asic or host
(mode dependent).
− − −
Digital power.
I/O Hu 13Xs GPIO[0] or from secondary EXTIA SOUT to DSP.
−
O 13Xs GPO[31] or a signal to the secondary ext. IA (SIN pin) from the DSP.
I/O Hu 13Xs GPIO[37] or a signal from the ext. IA to a DSP status register.
−
O 13Xs A reset from the DSP to the ext. IA (POR pin).
−
O 13Xs A signal from the DSP to the ext. IA (MCLK pin) or ext. modem chip
select.
I/O H 13Xs A signal from the ext. IA (ICLK pin) to the DSP.
I H 13Xs A signal from the primary ext. IA (SOUT pin) to the DSP or ext.
modem interrupt input.
−
O 13Xs A signal to the primary ext. IA (SIN pin) from the DSP.
I/O H 13Xs A signal to the ext. IA (CTRL1 pin) from the DSP.
I/O H 13Xs A signal from the ext. IA (FSYNC pin) to the DSP.
− − −
Ground for PLL.
−
O 13Xs Test clock, used to synchronize ext. logic.
−
I Hu External non-maskable input (NMI).
−
O 13Xs Read strobe.
−
O 13Xs Write strobe.
I/O Hu 13Xs Indicates a CPU op code fetch cycle or GPO[20].
−
O 13Xs ROM chip select.
−
O 13Xs I/O chip select or GPO[21].
− − −
Digital ground.
−
I OSC0 32.256MHz crystal oscillator input.
−
O OSC0 32.256MHz crystal oscillator output.
− − −
Digital power.
−
O 13Xs Programmable print motor control pin or GPO[3].
−
O 13Xs Programmable print motor control pin or GPO[2].
−
O 13Xs Programmable print motor control pin or GPO[1].
−
O 13Xs Programmable print motor control pin or GPO[0].
−
O 13Xs Programmable scan motor control pin or GPO[7].
−
O 13Xs Programmable scan motor control pin or GPO[6].
−
O 13Xs Programmable scan motor control pin or GPO[5].
−
O 13Xs Programmable scan motor control pin or GPO[4].
−
O 13Xs Register select cycle/dma cycle or GPO[18] and sxin clock divider
config. during reset.
I/O Hu 13Xs Wait state/halt state indication or GPO[19] and sxin lock divider config.
during reset.
− − −
Power for PLL.
I/O Tu 13Xs CPU data bus.
I/O Tu 13Xs CPU data bus.
I/O Tu 13Xs CPU data bus.
I/O Tu 13Xs CPU data bus.
5 – 5
Pin Description