Sharp UP-3300 Service Manual page 45

Pin
Name UP-3300
NO.
131 /CSC /CS3
132 TRNDTC TXD3
133 /DTRC /DTR3
134 /RTSC /RTS3
135 RCVDTC RCVDT3
136 /CTSC GND
137 /DSRC /DSR3
138 TRNRDYC TRNRDY3
139 RCVRDYC RCVRDY3
140 TRNEMPC TRNEMP3
141 SYCBKC NC
142 VCC VCC
143 GND GND
144 /CSD VCC
145 TRNDTD NC
146 /DTRD NC
147 /RTSD NC
148 RCVDTD GND
149 /CTSD GND
150 /DSRD GND
151 TRNRDYD NC
152 RCVRDYD NC
153 TRNEMPD NC
154 SYCBKD NC
155 /WIN /WRH
156 /RIN /RDH
157 RSLCT0 AH0
158 RSLCT1 AH1
159 RST RES USART
160 MCLK CLK USART
I TTL input
ID TTL input with pull down
IS TTL Schmidt input
ISU TTL Schmidt input with pull up
IO TTL I/O
3S 3-state Buffer (6mA)
ON6 Open drain (6mA)
2-4. Z80 CPU
1) Features
The extensive instruction set contains 158 instructions, including the
8080A instruction set as a subset.
•
NMOS version for low cost high performance solutions, CMOS
version for high performance low power designs.
•
Z0840006 - 6.17 MHz
•
CMOS Z84C0006 - DC to 6.17 MHz, Z84C008 - DC to 8 MHz,
Z84C0010 - DC to 10 MHz, Z84C0020 - DC - 20 MHz
•
6 MHz version can be operated at 6.144 MHz clock.
I/O Description
IS USART_C chip select
O RS-232 transmission
data signal
O RS-232 data terminal
ready signal
O USART_C
request to send
IS RS-232 reception
data signal
IS GND
IS RS-232 data set
ready signal
O RS-232 data
transmission enable
signal
O RS-232 data
reception enable
signal
O RS-232 transmission
buffer empty signal
IO NC
+5V
GND
IS USART_D chip select
O NC
O NC
O NC
IS GND
IS GND
IS GND
O NC
O NC
O NC
IO NC
I Write signal
I Read signal
I Address bus
I Address bus
IS Reset signal
I
•
The Z80 microprocessors and associated family of peripherals can
be linked by a vectored interrupt system. This system can be
daisy-chained to allow implementation of a priority interrupt
scheme.
•
Duplicate set of both general-purpose and flag registers.
•
Two sixteen-bit index registers.
•
Three modes of maskable interrupts:
Mode 0 — 8080A similar;
Mode 1 — Non-Z80 environment, location 38H;
Mode 2 — Z80 family peripherals, vectored interrupts.
•
On-chip dynamic memory refresh counter.
SYSTEM
CONTROL
CPU
CONTROL
CPU
BUS
CONTROL
2) Pin configuration
44
1
CLK
D4
D3
D5
D6
+5V
D2
D7
D0
D1
NC
11
12
44 pin Quad Flat Pack (QFP), Pin Assignments
(Only available for 84C00)
7 – 12
M1 A0
A1
MREQ A2
IORQ
A3
RD
A4
WR
A5
A6
RFSH
A7
A8
HALT
A9
A10
WAIT
A11
Z8400
A12
Z80 CPU
INT
A13
NMI
A14
A15
RESET
D0
D1
BUSREQ
BUSACK D2
D3
CLK
D4
+5V
D5
GND
D6
D7
Figure 1. Pin functions
34
Z80 CPU
22
ADDRESS
BUS
DATA
BUS
33
NC
A5
A4
A3
A2
A1
A0
GND
RFSH
M1
RESET
23