Sharp UP-3300 Service Manual page 46

3) General description
The CPUs are fourth-generation enhanced microprocessors with ex-
ceptional computational power. They offer higher system throughput
and more efficient memory utilization than comparable second- and
third-generation microprocessors. The internal registers contain 208
bits of read/write memory that are accessible to the programmer.
These registers include two sets of six general-purpose registers
which may be used individually as either 8-bit registers or as 16-bit
register pairs. In addition, there are two sets of accumulator and flag
registers. A group of "Exchange" instructions makes either set of
main or alternate registers accessible to the programmer. The alter-
nate set allows operation in foreground-background mode or it may
be reserved for very fast interrupt response.
The CPU also contains a Stack Pointer, Program Counter, two index
registers, a Refresh register (counter), and an Interrupt register. The
CPU is easy to incorporate into a system since it requires only a
single +5V power source. All output signals are fully decoded and
timed to control standard memory or peripheral circuits; the CPU is
supported by an extensive family of peripheral controllers.
The internal block diagram (Figure 3) shows the primary functions of
the processors. Subsequent text provides more detail on the I/O con-
troller family, registers, instruction set, interrupts and daisy chaining,
and CPU timing.
INSTRUCTION
DECODER
+5V
GND
CLOCK
CPU
TIMING
CONTROL
8 SYSTEMS 5 CPU
AND CPU CONTROL
CONTROL INPUTS
OUTPUTS
Figure 3. Z80C CPU Block Diagram
4) Pin description
Pin Signal
Symbol In/Out
No. name
1 CLK CLK In
2 D4 S D4 In/Out Data bus
3 D3 S D3 In/Out Data bus
4 D5 S D5 In/Out Data bus
5 D6 S D6 In/Out Data bus
6 +5V VCC —
7 D2 S D2 In/Out Data bus
8 D7 S D7 In/Out Data bus
9 D0 S D0 In/Out Data bus
10 D1 S D1 In/Out Data bus
11 NC NC —
12 INT S INT In
13 NMI VCC —
14 HALT VCC —
15 MREQ S MRQ Out
16 IORQ S IORQ Out
17 NC NC —
8-BIT
DATA BUS
DATA BUS
INTERFACE
INSTRUCTION
INTERNAL DATA BUS
REGISTER
REGISTER
ARRAY
CPU
TIMING
ADDRESS
LOGIC AND
BUFFERS
16-BIT
ADDRESS BUS
Function
Clock
+5V
NC
Interrupt request signal
Non-maskable interrupt signal
+5V
Memory request signal
Input / Output request signal
NC
Pin
Symbol
No.
18 RD
19 WR
20 BUSAK BUSAK
21 WAIT
22 BUSRQ BUSRQ
23 RESET
24 M1
25 RFSH
26 GND
27 A0
28 A1
29 A2
30 A3
31 A4
32 A5
33 NC
34 A6
35 A7
36 A8
37 A9
38 A10
39 NC
40 A11
41 A12
ALU
42 A13
43 A14
44 A15
2-5. Z80 CTC
1) Features
•
Four independently programmable counter/timer channels, each
with a readable downcounter and a selectable 16 or 256 prescaler.
Downcounters are reloaded automatically at zero count.
•
Selectable positive or negative trigger initiates timer operation.
•
Three channels have Zero Count/Timeout outputs capable of driv-
ing Darlington transistors. (1.5mV @ 1.5V)
•
NMOS version for cost sensitive performance solutions.
•
CMOS version for the designs requiring low power consumption
•
NMOS Z0843004 - 4 MHz, Z0843006 - 6.17 MHz.
•
CMOS Z84C3006 - DC to 6.17 MHz, Z84C3008 - DC to 8 MHz,
Z84C3010 - DC to 10 MHz
•
Interfaces directly to the Z80 CPU or—for baud rate generation—
to the Z80 SIO.
•
Standard Z80 Family daisy-chain interrupt structure provides fully
vectored, prioritaized interrupts without external logic. The CTC
may also be used as an interrupt controller.
•
6 MHz version supports 6.144 MHz CPU clock operation.
2) General description
The Z80 CTC, hereinafter referred to as Z80 CTC or CTC, four-chan-
nel counter/timer can be programmed by system software for a broad
range of counting and timing applications. The four independently
programmable channels of the Z80 CTC satisfy common microcom-
puter system requirements for event counting, interrupt and interval
timing, and general clock rate generation.
System design is simplified because the CTC connects directly to
both the Z80 CPU and the Z80 SIO with no additional logic. In larger
systems, address decoders and buffers may be required.
7 – 13
Signal
In/Out
name
S RDS Out Rread signal
S WRS Out Write signal
Out Bus acknowledge signal
S WAIT In Wait signal
In Bus request signal
S RES In Reset signal
S M1 Out Machine cycle one signal
NC — NC
GND — GND
S A0 Out Address bus
S A1 Out Address bus
S A2 Out Address bus
S A3 Out Address bus
S A4 Out Address bus
S A5 Out Address bus
NC — NC
S A6 Out Address bus
S A7 Out Address bus
S A8 Out Address bus
S A9 Out Address bus
S A10 Out Address bus
NC — NC
S A11 Out Address bus
S A12 Out Address bus
S A13 Out Address bus
S A14 Out Address bus
S A15 Out Address bus
Function