Sharp UP-3300 Service Manual page 47

D0
D1
D2
CPU
D3
DATA
D4
BUS
D5
D6
D7
CE
CS0
CTC
CS1
CONTROL
FROM
M1
CPU
IORQ
RD
DAISY
IEI
CHAIN
IEO
INTERRUPT
INT
CONTROL
CLK
Figure 1. Pin Functions
Programming the CTC is straightforward: each channel is pro-
grammed with two bytes: a third is necessary when interrupts are
enabled. Once started, the CTC counts down, automatically reloads
its time constant, and resumes counting. Software timing loops are
completely eliminated. Interrupt processing is simplified because only
one vector need be specified: the CTC internally generates a unique
vector for each channel.
The Z80 CTC requires a single +5% V power supply and the standard
Z80 single-phase system clock. It is packaged in 28-pin DIPs, a
44-pin plastic chip carrier, and a 44-pin Quad Flat Pack. (Figures 2a,
2b, and 2c). Note that the QFP package is only available for CMOS
versions.
3) Pin configuration
33
34
NC
CSI
CLK/TRG3
CLK/TRG2
NC
NC
CLK/TRG1
CLK/TRG0
NC
+5V
NC
44
1
Figure 2c. 44-pin Quad Flat Pack Pin Assignments
4) Functional description
The Z80 CTC has four independent counter/timer channels. Each
channel is individually programmed with two words: a control word
and a time-constant word. The control word selects the operating
mode (counter or timer), enables or disables the channel interrupt,
and selects certain other operating parameters. If the timing mode is
selected, the control word also sets a prescaler, which divides the
system clock by either 16 or 256. The time-constant word is a value
from 1 to 256.
CLK/TRG0
ZC/TO0
CLK/TRG1
ZC/TO1
CHANNEL
SIGNALS
CLK/TRG2
ZC/TO2
CLK/TRG3
RESET
Z80 CTC
+5V GND
23
2 2
CMOS
Z80 CTC
1 2
1 1
During operation, the individual counter channel counts down from
the preset time constant value. In counter mode operation the counter
decrements on each of the CLK/TRG input pulses until zero count is
reached. Each decrement is synchronized by the system clock. For
counts greater than 256, more than one counter can be cascaded. At
zero count, the down-counter is automatically reset with the time
constant value.
The timer mode determines time intervals as small as 2 µs (8 MHz), 3
µs (6 MHz), or 4 µs (4 MHz) without additional logic or software timing
loops. Time intervals are generated by dividing the system clock with
a prescaler that decrements a preset down-counter.
Thus, the time interval is an integral multiple of the clock period, the
prescaler value (16 or 256), and the time constant that is preset in the
down-counter. A timer is triggered automatically when its time con-
stant value is programmed, or by an external CLK/TRG input.
Three channels have two outputs that occur at zero count.
The first output is a zero-count/timeout pulse at the ZC/TO output.
The fourth channel (Channel 3) does not have a ZC/TO output; inter-
rupt request is the only output available from Channel 3.
The second output is Interrupt Request (INT), which occurs if the
channel has its interrupt enabled during programming. When the Z80
CPU acknowledges Interrupt Request, the Z80 CTC places an inter-
rupt vector on the data bus.
The four channels of the Z80 CTC are fully prioritized and fit into four
configuous slots in a standard Z80 daisy-chain interrupt structure.
Channel 0 is the highest priority and Channel 3 the lowest. Interrupts
can be individually enabled (or disabled) for each of the four chan-
nels.
5) Pin description
Pin
Symbol
No.
1 D0
2 D1
3 D2
4 D3
5 NC
6 NC
7 NC
8 D4
9 D5
10 D6
IEO
11 NC
IORQ
12 D7
NC
13 GND
ZC/TO2
14 RD
ZC/TO1
NC 15 NC
ZC/TO0
16 ZC/TO0
NC
17 NC
RD
18 ZC/TO1
GND
19 ZC/TO2
D7
20 NC
21 IORQ
22 IEO
23 INT
24 NC
25 IEI
26 NC
27 M1
28 NC
29 CLK
30 NC
31 CE
32 RESET
33 CS0
7 – 14
Signal
In/Out
name
S D0 In/Out Data bus
S D1 In/Out Data bus
S D2 In/Out Data bus
S D3 In/Out Data bus
NC — NC
NC — NC
NC — NC
S D4 In/Out Data bus
S D5 In/Out Data bus
S D6 In/Out Data bus
NC — NC
S D7 In/Out Data bus
GND — GND
S RDS In Read cycle status signal
NC — NC
S TM0 Out Zero count / Timeout signal
NC — NC
NC — NC
NC — NC
NC — NC
S IORQ In Input / Output request signal
NC — NC
S INT Out Interrupt request signal
NC — NC
VCC — +5V
NC — NC
S M1 In Machine cycle one signal
NC — NC
CLK In System clock
NC — NC
S A6 In Chip enable signal
S RES In Reset signal
S A0 In Channelselect signal
Function