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13.
2.
5
Interrupt Circuit
This c
ircuit
generate
s
three
interrupts
(EXTINT,
IN
TVDP,
and
INTEXV)
to
be
applied to the
CPU.
(1)
EXTINT
is
an
interrupt
request
signal
applied
from an
external
source
via
a
slot.
(2)
By
using the
VDP
interrupt
function
once
every l/50th second
by
th e
interrup
t
routine
supported
by
MSX
BASIC,
INTVDP
processes
key
inputs
by
key
scanning of the keyboard.
The
CPU
internal
timer
is
also
activated
by
this
input every
l/50th second
to
provide clock
signals.
This routine
is
also
employed
in
proces-
sing
inputs
from
the
SUPERIMPOSE, VIDEO,
and
COMPUTER
keys (unique Pioneer
fea-
tures).
(3)
INTEXV
generates
an
interrupt
when
the
external video
signal
is
stopped during
super-
impose
or
external
video
mode,
thereby
enabling switching
from
external to
internal
synchronization
without
picture disturbance.
Fig.
13-5
Interrupt
circuit
13.
2.
6
Address Bus
Due
to
fan-out
reasons,
the address
bus
is
connected
directly
to the
ROM/RAM
circuits,
but
via
buffers
74LS367
(IC6
thru IC8) to other
circuits.
ADDRESS
13. 2..7
Data Bus
The
data bus
is
connected
to the various LSIs,
ICs,
and
cartridge
connectors
via
a
bidirectional
buffer
74LS245
(IC9).
Bidirectional buffers control
the data
direction
depending
on
whether
data
is
applied to
or
receiv-
ed
from
the
CPU,
this
control being
executed
via
the
DIR
pin
in
IC9.
Data
can
be
passed
from
the
CPU
to the data
bus
when
an
H
level signal
is
applied to
the
DIR
pin,
and
can be passed
in
the
reverse direction
when
an
L
level signal
is
applied.
The
control
sign
al
appl
ied to
the
DIR
pin
is
formed
by
ED, Ml,
and
IORQ.
L
is
ap
plied
to
DI
R
(bus to
CPU) when RD,
or
both
Ml
and
IORQ
are at
L
level,
and
H
is
applied
(CPU
to bus)
in
all
other
cases.
Fig.
13-7
Data bus
13.
2.
8
Control Line
RD,
WR,
and
other
control
signals
from
the
CPU
are
con
nected
t
o
the
vari
ous
c
ircuits
via
buffer
LS367.
DRFSH,
DMERQ,
and
DRD
are
passed
directly
to
the
slot
and
RAM
selector
circuits
bypassing the buffer to speed
up
slot
selection
and
RAM
accessing.
Fig.
13-8 Control
line
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