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13.8
PSG
{PROGRAMMABLE SOUND
GENERATOR)
The
PSG
(IC5)
circuit
is
the
Yamaha
YM-2149.
This
LSI
is
up
compatible with the
higher ranking
AY-3-8910 from
the
GI
Company,
and
features a
clock
frequency
divider
(1/2) to
enable
direct
input of the
system
clock.
The
PSG
has
three
independent
sound
outputs A,
B,
and
C
which
are
connected
to
left
and
right
channels
by
a
matrix
circuit in
the
PX-7
for
output
to speakers
via
a
mixing
amplifier
(IC110)
and power
amplifiers
(IC111 and
IC112).
And
in
addition to a
sound
generator function,
this
LSI
also
features
two
8-bit
parallel
I/O
ports
(IOA and
IOB)
used
in
a control-
ler
I/F for joystick
and
tablet
connections.
The
PSG
is
accessed
by
BDIR
and
BC1
with
BC2
and
A8
at
H
level
and
A9
at
L
level.
(A2
is
applied
to
the
A9
input
to
prevent generation of address
images.)
BDIR
and
BC1
are
both changed
to
H
by
writing
the I/O address
AO
(H),
and
the
register
address
is
then
latched
by
the
PSG. Data
writing
is
executed
when
BDIR
is
changed
to
H
with
BC1
remaining
at
L
by A1(H)
writing,
and
data
reading
is
executed
when BC1
is
changed
to
H
with
BDIR
remaining
at
L
by A2(H)
reading.
The
timing
for
these operations
is
outlined
in Fig.
13-36
Fig.
13-35
PSG
circuit
<B
DIR
AND
BC1
CONTROL
CHART)
(AO
(H)
W
-»
ADDRESS
LATCH)
(A1
(H)
W
-
DATA
WRITING)
(A2
(H)
R
-*
DATA
READING)
APART FROM THE
ABOVE,
BDIR
AND
BC1
ARE ALWAYS AT
L
Fig.
13-36
PSG
BDIR,
BCI
control chart
SB
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