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13.
7.
2
Cassette Interface Section
•
Input
circuit
When
the
PPI
pin
13
CASON
output
is
changed
to
H
level,
Q2
is
turned
off
and
relay
RY1
is
put
into
break
status.
In
this
condition,
REM+/—
is
open and
the
cassette
recorder
motor
is
stopped.
The
IC33(2/2)
output
is
connected
to
the
IC33(l/2) comparator input
via
a
clamp
circuit (to
prevent
excessive inputs) consisting of
R34, D4,
D3, C33, and C34,
thereby
resulting
in
input of
LD
DATA
to
IC33(l/2).
The
IC33(2/2)
CPE
interface
serves
as
an
amplifier to
ensure
that
the
LD
DATA
is
at
the
same
level
as
the
CMT
IN
signal.
IC33(l/2)
also
forms
a
schumitt
amplifier
with
positive feed-
back
via
R27
and R26.
When
the PPI
pin
13
CASON
output
is
changed
to
L
level,
Q2
is
turned
on
and
the
relay
is
put
into
make
status.
REM+/—
is
shorted
and
the
motor
is
switched on,
resulting in
the input
from
CMT
IN
being applied
to
IC33(l/2).
• Output
circuit
The
PPI
pin
12
CASW
(PC5) output
is
passed
via
a
bandpassfilter consisting of
C30, C31,
and
R22
thru
R24,
resulting
in
an
output
quasi-audio
signal
being passed
to
CMT
OUT.
AUDIO
CASSETTE
INTERFACE
C36
+!
13.
7.
3
Keyboard
l/F
The number
of
leads
in
the connecting
cable to
the separated
keyboard
is
reduced
by
using
a
partially
bidirectional
bus
line.
The
bidirectional section
of
the
bus
line
includes
KXO, KX1, KX2, KX4,
and
YA
thru
YD,
thereby
reducing the
number
of
leads
in
a
bus
line
requiring
17
leads
to 13.
Bus
line
control involves enabling
IC45
by
scan data
output
passed
from
the
CPU
to
the
PC
port,
and
passing
YA
thru
YD
to the bus.
Bus
collisions
are
avoided
by
disabling
U2
in
advance.
IC45
is
disabled
after
YA
thru
YD
is
latched
by
U4.
This
is
followed
by
enabling
U2,
passing
the
XO, XI, X2, and
X4
key
inputs to
the
bus,
and
reading
from
the
PB
port.
The
reason
for
delay
1
is
to enable
1C45
until
YA
thru
YD
has
been completely
latched
by
U4.
And
the reason
for
delay 2
is
to
enable
U2
after
IC45
has
been
disabled.
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