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13.
6
VDP
(VIDEO DISPLAY PROCESSOR)
The
VDP
(TMS9129NL)
is
accessed
at
V
DP=L
with data
transfer
being
controlled
by
CSW,
CSR,
and
M
ODE.
CSW:
Write
signal
changed
to
L when
data
is
written
from
CPU
to
VDP
CSR:
Read
signal
changed
to
L
when
data
is
read
from
CPU
to
VDP
MODE:
L
level
when
reading/writing
V-RAM
to/from
CPU, and
H
in
other
cases.
CPU
address
AO
is
normally connected
to
MODE,
and
the
VDP
and
V-RAM
are accessed
separately
depending on the
AO
value
when
the
VDP
is
accessed.
Table
13-6
Direc
t
writ
ing
from
CPU
to
V-RAWI
(data
set
at
CSW
leading edge)
Direct reading of
V-RAM
data
to
CPU
Writing
from
CPU
to
VDP
Reading
of
VDP
status
to
CPU
The
RESET/SYN
C
input
i
s
(1)
OV
when
RESET
is
L,
(2)
5V
when
RESET
is
H
and
SYNC
is
L
(+12
V
divid
ed
by
R12
and
R13),
(3)
and
12V
when
RESET
and
SYNC
are
both H.
Table
13-7
resIt
SYNC
RESET/SYNC
When
reset
(when power
is
switched
on
or
when
RESET
switch
is
pressed)
During normal
operatio
When
external
synchronizing
signal
SYNC
is
applied
during
superimpose
or external
video
(1)
With
RESET/SYNC
leading edges serving
as
horizontal
synchronizing
pulses,
the
VDP
internal
counter
is
reset in
a
horizontal synch-
ronous
state.
(2)
And
with synchronizing
pulses greater
than
7.2
nsec
serving as
vertical
synchronizing
pulses,
the
internal
vertical
counter
is
set in
a
vertical
synchronous
state.
(3)
The INT
output
(VDP
interrupt
signal)
genera-
tes
L
level
pulses
at
the
end of each
display
screen scanning operation
(that
is,
at
every
l/50th
se
c sy
nchro
nized with
VSYNC).
And
as
INTVDP,
the
INT
output
is
also
connected
to
the
CPU
interrupt
pin to be used
as
a l/50th
sec
timer
interrupt.
Fig.
13-27
RESET/SYNC
input
waveform
The
VDP
clock
(10.68MHz)
rectifies
the
CLK
signal
at
R74, D23, and C55,
this
then
being
applied to
XTAL
1
of
VDP
via
an
inverter at a
duty
of almost
50%.
A
16K
byte
V-RAM
memory
is
formed
by
two
16K
X
4-bit
DRAMs
(TMS4
416-15NL
equivalent).
This
V-RAM
is
accessed
by RAS, CAS,
and
WE
in
the
same
way
as
the
main
RAM.
Fig.
13-28
VDP
circuit
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