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Table 3-5. Timing condition of On-chip supporting modules
Characteristics
DMA
DREQ setup time
DREQ hold time
TEND delay time 1
TEND delay time 2
ITU
Timer outputdelay time
Timer input setup time
Timer clock input setup
time
Timer clock pulse width
(single edge)
Timer clock pulse width
(both edge)
3-18 In-Circuit Emulation
(Vcc = 5.0V, f = 16MHz)
H8/3003
Symbol
Vcc = 5V
f = 16MHz
min
max
t
30
-
DRQS
t
10
-
DRQH
t
-
50
TED1
t
-
50
TED2
t
-
100
TOCD
t
50
-
TICS
t
50
-
TCKS
t
1.5
-
TCKWH
t
2.5
-
TCKWL
Probe Type
HP 64784E
HP 64784D
+
HP 64784x
typ *1
worst typ *1 worst
-
65.9
-
-
-6.0
-
-
61.6
-
-
61.6
-
-
111.6
-
-
85.9
-
-
85.9
-
-
-
-
-
-
-
Unit
59.7
ns
-1.1
ns
59.0
ns
59.0
ns
109.0
ns
79.7
ns
79.7
ns
-
tcyc
-
tcyc
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