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Table 3-8. Timing condition of On-chip supporting modules
Characteristics
ITU
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse width
(single edge)
Timer clock pulse width
(both edge)
SCI
Input clock cycle(Async)
Input clock cycle(Sync)
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Received data setup time
Received data hold time (Clock
input)
3-24 In-Circuit Emulation
(Vcc = 3.0V, f = 10MHz)
H8/3003
Symbol
Vcc = 3V
f = 10MHz
min
t
-
TOCD
t
50
TICS
t
50
TCKS
t
1.5
TCKWH
t
2.5
TCKWL
t
4
SCYC
t
6
SCYC
t
-
SCKr
t
-
SCKf
t
0.4
SCKw
t
-
TXD
t
100
RXS
t
100
RXH
Probe Type
HP 64797B
+
HP 64784x
max
typ *1
worst
100
-
111.6
-
-
88.1
-
-
88.1
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
0.6
-
-
100
-
106.6
-
-
138.8
-
-
109.2
Unit
ns
ns
ns
tcyc
tcyc
tcyc
tcyc
tcsyc
tscyc
tscyc
ns
ns
ns
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