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Appendix 3
List of buffer memory addresses
The following table lists the buffer memory addresses of the high-speed counter module. For details on the buffer memory
addresses, refer to the following.
Page 62 Details of buffer memory addresses
Do not write any data to the system area or the area whose data type is monitor in the buffer memory. Writing
any data in those areas may cause a malfunction.
Address
Decimal (hexadecimal)
CH1
CH2
0 (0H)
32 (20H)
1 (1H)
33 (21H)
2 (2H)
34 (22H)
3 (3H)
35 (23H)
4 (4H)
36 (24H)
5 (5H)
37 (25H)
6 (6H)
38 (26H)
7 (7H)
39 (27H)
8 (8H)
40 (28H)
9 (9H)
41 (29H)
10 (0AH)
42 (2AH)
11 (0BH)
43 (2BH)
12 (0CH)
44 (2CH)
13 (0DH)
45 (2DH)
14 (0EH)
46 (2EH)
15 (0FH)
47 (2FH)
16 (10H)
48 (30H)
17 (11H)
49 (31H)
18 (12H)
50 (32H)
19 (13H)
51 (33H)
20 (14H)
52 (34H)
21 (15H)
53 (35H)
22 (16H)
54 (36H)
23 (17H)
55 (37H)
24 (18H)
56 (38H)
25 (19H)
57 (39H)
26 (1AH)
58 (3AH)
27 (1BH)
59 (3BH)
28 (1CH)
60 (3CH)
29 (1DH)
61 (3DH)
30 (1EH)
62 (3EH)
31 (1FH)
63 (3FH)
64 to 255 (40H to FFH)
256 (100H)
272 (110H)
257 (101H)
273 (111H)
258 (102H)
274 (112H)
259 (103H)
275 (113H)
260 (104H)
276 (114H)
APPENDICES
60
Appendix 3 Buffer Memory Areas
Buffer Memory Areas
Name
CH Preset value setting (L)
CH Preset value setting (H)
CH Present value (L)
CH Present value (H)
CH Coincidence output point No.1 setting (L)
CH Coincidence output point No.1 setting (H)
CH Coincidence output point No.2 setting (L)
CH Coincidence output point No.2 setting (H)
CH Overflow detection
CH Counter function selection setting
CH Sampling/cycle time setting
CH Sampling/cycle counter flag
CH Latch count value (L)
CH Latch count value (H)
CH Sampling count value (L)
CH Sampling count value (H)
CH Cycle pulse count previous value (L)
CH Cycle pulse count previous value (H)
CH Cycle pulse count current value (L)
CH Cycle pulse count current value (H)
CH Ring counter lower limit value setting (L)
CH Ring counter lower limit value setting (H)
CH Ring counter upper limit value setting (L)
CH Ring counter upper limit value setting (H)
CH Cycle pulse count difference value (LL)
CH Cycle pulse count difference value (LH)
CH Cycle pulse count difference value (HL)
CH Cycle pulse count difference value (HH)
CH Counter function update flag
CH Signal monitor
CH Synchronization latch count value (L)
CH Synchronization latch count value (H)
System area
CH PWM output cycle time setting (L)
CH PWM output cycle time setting (H)
CH PWM output ON time setting 1 (L)
CH PWM output ON time setting 1 (H)
CH PWM output ON time setting 2 (L)
Default value
Data type
0
Setting
0
Setting
0
Monitor
0
Monitor
0
Setting
0
Setting
0
Setting
0
Setting
0
Monitor
0
Setting
0
Setting
0
Monitor
0
Monitor
0
Monitor
0
Monitor
0
Monitor
0
Monitor
0
Monitor
0
Monitor
0
Monitor
0
Setting
0
Setting
0
Setting
0
Setting
0
Monitor
0
Monitor
0
Monitor
0
Monitor
0
Monitor
Depends on external
Monitor
signal status
0
Monitor
0
Monitor
FFFFH
Control
7FFFH
Control
0
Control
0
Control
0
Control
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