Motorola CPCI-6020 Installation And Use Manual page 90

Harrier Power-Up Configuration
Table 4-2 Harrier Power-Up Configuration Settings (continued)
Harrier
XAD Bus Select
Signal Option
XAD Jumpers
[23:20]
XAD[19] Resistor
XAD[18] Resistor
XAD[17] Fixed
XAD Fixed
[16:15]
XAD On board
logic sets
[14-12]
ratio
XAD Fixed
[11:10]
XAD[9] Jumper
on board
XAD Resistor
[8:7]
XAD[6] Fixed
XAD Fixed
[5:4]
XAD[3] Fixed
XAD Fixed
[2:1]
XAD[0] Fixed
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Power Up
Default Register Bit(s)
1111 XCSR.GCSR.PUST
[3:0]
0 State of bit can be
inferred:
XCSR.CLAS
(XCSR+$308)
1 XCSR.PARB.ENA
A=1 XCSR.XARB.ENA
B=0
A=00 XCSR Register
Group Base
B=01
Address
000 XCSR.GCSR.RAT
001
010
011
100
101
110
111
A=01 XCSR.XPAT0.DW
B=XX
A=1 XCSR.XPAT0.RVEN
B=0
A=01 XCSR.XPAT1.DW
B=xx
A=1 XCSR.XPAT1.RVEN
B=0
A=00 XCSR.XPAT2.DW
B=xx
0 XCSR.XPAT2.RVEN
xx XCSR.XPAT2.DW
0 XCSR.XPAT3.RVEN
Functional Description
Meaning of Power-Up
Default State
Generic Power Up Status Bits
(Software readable header)
Set PCI Configuration register CLAS to
present class code for "bridge device".
Enable internal PCI arbiter
Harrier A, enable internal PPC arbiter
Harrier B, disable internal PPC arbiter
Harrier A XCSR base addr. $FEFF0000
Harrier B XCSR base addr. $FEFF1000
Reserved
PPC-to-PCI clock ratio 3:2
PPC-to-PCI clock ratio 2:1
PPC-to-PCI clock ratio 5:2
PPC-to-PCI clock ratio 1:1
Reserved
PPC-to-PCI clock ratio 3:1
Reserved
Harrier A, Flash Bank A 16-bits wide
Harrier B, Flash Bank A not used.
Harrier A, Flash Bank A is Reset Vector.
Harrier B has no flash.
Harrier A, Flash Bank B to 16-bit width
Harrier B, Flash Bank B not used.
Harrier A, Flash Bank B is Reset Vector
if and only if Bank A is not Reset Vector.
Harrier B has no flash.
Harrier A, Xport Ch. 2 8-bit width.
Harrier B, Xport Ch. 2 not used.
Disable Xport channel 2 as Reset Vector
Xport Channel 3 Data Width
Unused.
Disable Xport channel 3 as Reset Vector
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