Trlys#F Diagnostics - GE Mark VIeS System Manual

6.7.5 TRLYS#F Diagnostics

Diagnostic tests to components on the terminal boards are as follows:
• The voltage to each relay coil is monitored and checked against the command at the frame rate. If there is no agreement
for five consecutive frames, an alarm is latched.
• The voltage across each solenoid power supply is monitored and if it goes below 16 V ac/dc, an alarm is created.
• If any one of the outputs goes unhealthy a composite diagnostic alarm, L3DIAG_xxxx occurs.
• Each terminal board connector has its own ID device that is interrogated by the I/O pack. The connector ID is coded into
a read-only chip containing the board serial number, board type, revision number, and the JR1/JS1/JT1 connector
location. When an ID chip is read by the I/O pack and a mismatch is encountered, a hardware incompatibility fault is
created.
The diagnostic signals can be individually latched, and then reset with the RSTDIAG signal if they go healthy.
160 GEH-6855_Vol_II GEH-6855_Vol_II Mark VIeS Functional Safety Systems Volume II
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