Main Signal Demodulation; Differential Decoding - NEC PASOLINK Training Course

ROI-S04488
2.4.2

Main Signal Demodulation

π
2.4.3

Differential Decoding

The incoming 70 MHz IF signal is amplified up to the required level by an
AGC amplifier and split into two separate signals for the P and Q channels
and then fed to the mixer. In addition to the 70 MHz IF signals, two
carriers having a phase difference of π/2 produced by the carrier recovery
circuit, which consists of a carrier synchronizer, a 70 MHz oscillator, and a
carrier splitter (π/2), are applied to the decision circuit. In the decision
circuit, each 70 MHz IF signal is coherent-detected with the related carrier
to represent the original baseband signal corresponding to the phase
assignment (see Fig. 2-4).
π/2
CARR 1
0
CARR 2
3π/2
Note: −1 is replaced by logic 0 and +1 by logic 1.
Fig. 2-4 Demodulation
The clock oscillator circuit generates a 38.383 MHz clock for the analog-
to-digital converter (A-D CONV) circuits. In the A-D CONV, two 38.383
Mbps data streams are regenerated with 38.383 MHz clock. Then the two
re-generated 38.383 data streams enter the differential decoding (DIFF
DECOD) circuit.
The process of differential decoding is the reverse of the differential
encoding at the transmitting end.
streams, the phase of the time slot leading one bit before an incoming time
slot is subtracted in quaternary notation from that of the incoming time
slot. The decoded 38.383 Mbps data streams are sent to the frame
synchronizer and descramblers on the DPU section of the MAIN BOARD
for receive digital processing.
FUNCTIONAL OPERATION
DETECTED OUTPUT
INPUT
PHASE
P CHANNEL
0 -1
π/2
-1
π
+1
3π/2 +1
In the natural binary-coded pulse
Q CHANNEL
-1
+1
+1
-1
2-21