Dsp56F807 Processor - Motorola Digital DNA DSP56F807 Hardware User Manual

Evaluation module
Table of Contents

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A
A[0..15]
A0
A1
A2
A3
A4
A5
A6
4
A7
A8
A9
A10
A11
A12
A13
A14
A15
D[0..15]
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 8
D 9
D 1 0
D 1 1
D 1 2
D 1 3
3
D 1 4
D 1 5
/PS
/DS
/ W R
/ R D
/IRQA
/IRQB
EXTBOOT
XTAL
EXTAL
C L K O
/ R E S ET
/RSTO
TXD0
RXD0
2
TXD1
Primary serial_com
RXD1
Secondary PFC_PWM
T D 0
Primary PFC_PWM
T D 1
Primary PFC_ZERO_CROSSING
T D 2
Secondary ZERO_CROSSING
T D 3
Primary PFC_ENABLE
T C 0
Secondary PFC_ENABLE
T C 1
TDI
T D O
JTAG
T C K
/TRST
TMS
TCS
TCS
D E B U G _EVENT
MISO
M O S I
S C LK
/SS
1
A
B
U 1 A
1
4 0
PB0
A 0
M P I O B 0
USER LED: RED
2
4 1
PB1
USER LED: YELLOW
A 1
M P I O B 1
3
4 2
A 2
M P I O B 2
PB2
USER LED: GREEN
4
4 3
A 3
M P I O B 3
PB3
5
4 4
PB4
SERIAL D/A /CS
A 4
M P I O B 4
6
4 5
PB5
PRIMARY UNI-3 BRAKE CONTROL
A 5
M P I O B 5
7
4 6
PB6
SECONDARY UNI-3 BRAKE CONTROL
A 6
M P I O B 6
8
4 7
PB7
SECONDARY serial_con
A 7
M P I O B 7
1 0
A 8
1 1
4 9
USER JUMPER #1
A 9
M P I O D 0
P D 0
1 2
5 0
P D 1
USER JUMPER #2
A 1 0
M P I O D 1
1 3
5 1
P D 2
A 1 1
M P I O D 2
1 4
5 2
P D 3
GP PUSH BUTTON 1
A 1 2
M P I O D 3
1 5
5 3
P D 4
GP PUSH BUTTON 2
A 1 3
M P I O D 4
1 6
5 4
A 1 4
M P I O D 5
P D 5
START/STOP SW
1 7
A 1 5
7 5
P W MA0
Primary UNI-3 PWM 0
P W M A 0
2 3
7 7
P W MA1
Primary UNI-3 PWM 1
D 0
P W M A 1
2 4
7 8
P W MA2
Primary UNI-3 PWM 2
D 1
P W M A 2
2 5
7 9
D 2
P W M A 3
P W MA3
Primary UNI-3 PWM 3
2 6
8 0
D 3
P W M A 4
P W MA4
Primary UNI-3 PWM 4
2 7
8 1
P W MA5
Primary UNI-3 PWM 5
D 4
P W M A 5
2 8
1 2 3
ISA0
D 5
I S A 0
2 9
1 2 4
ISA1
D 6
I S A 1
3 0
1 2 5
D 7
I S A 2
ISA2
3 1
8 2
D 8
F A U L T A 0
F A U LTA0
3 2
8 3
F A U LTA1
D 9
F A U L T A 1
3 3
8 4
F A U LTA2
D 1 0
F A U L T A 2
3 5
8 5
F A U LTA3
D 1 1
F A U L T A 3
3 6
D 1 2
3 7
1 4 7
D 1 3
P H A 0
P H ASEA0
3 8
1 4 8
D 1 4
P H B 0
P H ASEB0
3 9
1 4 9
I N D E X0
D 1 5
I N D E X 0
1 5 0
H O M E 0
H O M E 0
1 9
P S
2 0
1 0 2
D S
A N A 0
1 0 3
A N A 1
2 1
1 0 4
W R
A N A 2
2 2
1 0 5
R D
A N A 3
1 0 6
A N A 4
6 9
1 0 7
I R Q A
A N A 5
7 0
1 0 8
I R Q B
A N A 6
1 0 9
A N A 7
8 6
9 9
+ 3 .3VA
X B O O T
V R H
9 2
5 7
P W MB0
Secondary UNI-3 PWM 0
X T A L
P W M B 0
9 3
5 8
E X T A L
P W M B 1
P W MB1
Secondary UNI-3 PWM 1
1 5 8
5 9
C L K O
P W M B 2
P W MB2
Secondary UNI-3 PWM 2
6 0
P W MB3
Secondary UNI-3 PWM 3
P W M B 3
9 8
6 1
P W MB4
Secondary UNI-3 PWM 4
R E S E T
P W M B 4
9 7
6 2
P W MB5
Secondary UNI-3 PWM 5
R S T O
P W M B 5
6 4
ISB0
I S B 0
1 5 9
6 6
T X D 0
I S B 1
ISB1
1 6 0
6 7
R X D 0
I S B 2
ISB2
7 1
F A U LTB0
Secondary UNI-3 OVER VOLTAGE
F A U L T B 0
5 5
7 2
F A U LTB1
Secondary UNI-3 PHASE A OVER CURRENT
T X D 1
F A U L T B 1
5 6
7 3
F A U LTB2
Secondary UNI-3 PHASE B OVER CURRENT
R X D 1
F A U L T B 2
7 4
F A U L T B 3
F A U LTB3
Secondary UNI-3 PHASE C OVER CURRENT
1 2 6
T D 0
1 2 7
1 5 1
P H ASEA1
T D 1
P H A 1
1 2 8
1 5 2
P H ASEB1
T D 2
P H B 1
1 2 9
1 5 4
I N D E X1
T D 3
I N D E X 1
1 5 5
H O M E 1
H O M E 1
1 3 0
T C 0
1 3 1
1 1 3
T C 1
A N A 8
1 1 4
A N A 9
1 3 6
1 1 5
TDI
A N A 1 0
1 3 7
1 1 6
T D O
A N A 1 1
1 3 4
1 1 7
T C K
A N A 1 2
1 3 2
1 1 8
T R S T
A N A 1 3
1 3 5
1 1 9
T M S
A N A 1 4
1 3 3
1 2 0
T C S
A N A 1 5
1 2 1
1 1 0
+ 3 .3VA
D E
V R H 2
1 4 5
1 3 9
M I S O
M S C A N _ T X
M S C A N_TX
1 4 6
1 4 2
M O S I
M S C A N _ R X
M S C A N _ R X
1 4 4
S C L K
1 4 3
S S
D S P 5 6F807FV80
B
Figure A-1. DSP56F807 Processor
C
Primary UNI-3 OVER VOLTAGE
Primary UNI-3 PHASE A OVER CURRENT
Primary UNI-3 PHASE B OVER CURRENT
Primary UNI-3 PHASE C OVER CURRENT
PRIMARY ENCODER
HALL EFFECT /
ZERO CROSSING
Primary U3_V_SENSE_DCB
A N 0
Primary U3_I_SENSE_DCB
A N 1
Primary U3_I/BK_EMF_SENSE_A
A N 2
A N 3
Primary U3_I/BK_EMF_SENSE_B
A N 4
Primary U3_I/BK_EMF_SENSE_C
A N 5
Primary U3_TEMP_SENSE
A N 6
A N 7
SECONDARY ENCODER
HALL EFFECT /
ZERO CROSSING
A N 8
Secondary U3_V_SENSE_DCB
Secondary U3_I_SENSE_DCB
A N 9
Secondary U3_I/BK_EMF_SENSE_A
A N 10
A N 11
Secondary U3_I/BK_EMF_SENSE_B
A N 12
Secondary U3_I/BK_EMF_SENSE_C
Secondary U3_TEMP_SENSE
A N 13
A N 14
A N 15
CAN
Title

DSP56F807 Processor

Document
Size
Number
B
Date:
C
D
U 1 B
1 8
9
V S S _ I O 1
V D D _ I O 1
4 8
3 4
V S S _ I O 2
V D D _ I O 2
7 6
6 3
V S S _ I O 3
V D D _ I O 3
9 5
9 4
V S S _ I O 4
V D D _ I O 4
1 5 7
1 5 3
V S S _ I O 5
V D D _ I O 5
1 4 1
1 4 0
V S S _ I O 6
V D D _ I O 6
9 1
8 9
V S S _ I O 7
V D D _ I O 7
9 0
V S S _ I O 8
1 2 2
9 6
V S S _ I O 9
V D D A _ C O R E 1
1 5 6
8 8
V P P
V D D A _ A R E G 1
6 8
V P P 2
1 1 1
+ 3 .3VA
V D D A _ A D C 1
1 0 0
V D D A _ A D C 2
C 8
8 7
V S S A _ A R E G 1
0.1uF
1 1 2
6 5
V S S A _ A D C 1
V C A P C 1
1 0 1
1 3 8
V S S A _ A D C 2
V C A P C 2
D S P 5 6F807FV80
C 1
2.2uF
R 1 24
T C S
1K
DSP Standard Products Division
(480) 413-5090
63A10516S
Monday, October 16, 2000
Designer:
DSPD Design
D
E
4
+3.3V
+3.3VA
C 7
0.1uF
3
+
+
C 2
2.2uF
2
2100 East Elliot Road
Tempe, Arizona 85284
1
FAX: (480) 413-2510
Rev.
1.0
Sheet
1
of
18
E

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