Mitsubishi Electric MELSEC-Q Structured Programming Manual page 78

FXCPU Structured Programming Manual
[Device & Common]
• 2-phase encoder generates outputs for the phase A and phase B with a phase difference of 90°. With
these outputs, a high speed counter automatically executes up-counting and down-counting as shown in
the figure below.
- When a counter is executing 1-edge counting
Phase A
Phase B
- When a counter is executing 4-edge counting
Phase A
Phase B
• The up/down-counting operation of C251 to C255 is indicated by the ON/OFF status of M8251 to M8255.
ON: Down-counting
OFF: Up-counting
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Phase A
+1
+1
Phase B
Up-counting Down-counting
+1 +1 +1 +1 +1
-1 -1 -1 -1 -1
Phase A
Phase B
+1 +1 +1 +1
Up-counting Down-counting
-1
-1
-1 -1 -1 -1
2 Devices in Detail
2.7 High Speed Counter [C]