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-
fbc: internal clock frequency, fixed by Bit Rate Filter setting (h'0E[D4:D1]BRF_Bit3..0)
-
Error margin is as same as the setting value of register: Err_Margin6..0.
- Calculation example
fp = 600Hz
fbc = 23.69kHz (Set the cutoff frequency of Bit Rate Filter as 619Hz)
Pre_Time8..0 = (2 x 23.69) / 0.6 = 78.9 à 79(h'18[D7], h'17[D7:D0] = b'001001111)
If the number of clocks is within "79±Err_Margin6..0". RF receiving signal will be recognized as Preamble signal.
Notice: 2
When to use the function of AutoOff Type A with using Preamble Detection, set both Data Comparator
Quick Charge 1 and 2 to the status of ON.
(In the settings of register: AutoOffA_en (h'10[D5] = "1") and register: Preamble_en (h'0F[D6] = "1"),
set register: Data Comparator Quick Charge 1 (h'10[D7] = "1") and register: Data Comparator Quick
Charge 2 (h'10[D6] = "1").)
If not set above, the function of AutoOff Type A may fail an expected operation. As the result, this IC
can't continue enough signal detection period and an valid data can't be get in some.
6.5.7
ASK Demodulation
To select ASK, set register:h'0A[D4] to "1"(ASK).
(1)
RSSI
Detect the level of IF signal.
(2)
AD converter (ADC)
Digitize the level of IF signal detected by RSSI.
(3)
LFP (ASK)
The cutoff frequency of LPF (fc) is about 40 kHz.
(4)
Limiter (This is only valid to use the function of Data Comparator Quick Charge 2.)
This is only valid to use the function of Data Comparator Quick Charge 2 in the subsequent Data
Comparator circuit. RSSI signal voltage through LPF is kept over the internal setting value in Limiter
circuit. Limit level is calculated with the peak voltage in the sequential. The peak voltage is detected
in Peak Hold Circuit in the subsequent of Bit Rate Filter.
- Peak Hold Circuit
Peak Hold Circuit outputs peak voltage to track its input (Bit Rate Filter output) with time constant
that is fast at the rising of the input signal and that is slow at the falling of the input signal. The time
constants are tp' / fbc at charging and tr / fbc at discharging.
* fbc: internal clock frequency set by Bit Rate Filter, register:h'0E [D4:D1]BRF_Bit3..0
* tp': inverse number of 1/tp + 1/tr
* tp: peak hold voltage charge coefficient, register:h'1C [D4:D3] Peak_Charge1..0
* tr: peak hold voltage discharge coefficient, register:h'1C [D7:D5] Peak_Ref2..0
When TC32306FTG starts to Run status, Peak Hold Circuit output voltage will reach 90% of the peak
voltage during "tp' / fbc x 2.30[s]".
Input Signal of Peak Hold
Circuit
During the signal rising
During the signal falling
Table 6-24 Setting of Peak Hold Circuit
Status
Viph - voph ≥ 0
Viph - voph < 0
Viph: Input voltage of Peak Hold Circuit
Voph: Output voltage of Peak Hold Circuit
26
Register to set time constant
h'1C[D4:D3]Peak_Charge1..0
h'1C[D7:D5]Peak_Ref2..0
h'1C[D7:D5]Peak_Ref2..0
TC32306FTG
2015-10-01
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