Advertisement
1.
Power On, and reset is released after the voltage supply becomes stable.
2.
Set registers if necessary with Standby (ENB pin = "H", register:h'0A[D7]ENB = "1",
register:h'0A[D6]ACT = "0"). Then internal regulators and Reference Clock Oscillator start to
operate.
3.
After the registers settings, set register:h'0A and move to Run.
(ENB pin = "H", register:h'0A[D7]ENB = "1", register:h'0A[D6]ACT = "1")
4.
The setup sequence and operation of internal function blocks will start after setting Delay time
from the output level of Reference Clock Oscillator is over a certain level.
5.
PLL Block will start after the internal setup (about 0.05 ms). After locking the expected frequency
is detected, PLL_LD signal and Internal LD Signal will be from "L" to "H". PLL lock-up time is
approximately 0.05 ms after internal setup is finished. About Internal LD Signal, see section
6.6.5.
6.
Input the signal for modulation to DATA_IO pin. The RF modulated Signal will be transmitted
from PA after PLL_LD signal turns to be "H" immediately, because initial value of
register:h'13[D1]PA_en is "1". It is also possible to set the register:h'13[D1]PA_en = "0" at the first
register setting.
Voltage Supply
ENB
RESET
Control Command
（SPI）
Internal Regulator
(voltage)
Starting the system
clock input to logic
circuit
Level of
Reference Clock
Internal Counter
PLL Block
PLL_LD Signal
: at DET_TMONI1 / 2 pin
Signal for Modulation
: at DATA_IO pin
RF Output Signal
: at PA_OUT pin
Fig 6-30 Example of Boot Sequence Timing Chart (SPI Mode / TX)
* The example of timing chart may be omitted or simplified for explanatory purposes.
In this example, ENB pin and voltage supply are connected.
Register Setting: h‛0A[D7]ENB="1", h‛0A[D6]ACT="0"
Register Setting: h‛0A[D7]ENB="1", h‛0A[D6]ACT="1"
Register
Settings
105.5µs
High Impedance
48
Delay Time Setting
* 105.5μs / 211.1μs / 316.5μs / 527.5μs / 949.5μs
0.05ms
Internal Setup
0.05ms
Lock Up
Deta Signal
Modulation
Output
TC32306FTG
*: Initial Value
It indicates typical.
2015-10-01
Advertisement
