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6.10.9 h'11 Charge2 Threshold Setting
D7
Name
Charge2_
Th7
Initial
0
Type
R/W
[D7:D0]Charge2_Th7..0 [Quick Charge 2 Threshold Level]
When to set Data Comparator Quick Charge 2 (h'10[D6]Charge2_en = "1") and FSK Demodulation (h'0A[D4]FSK_ASK = "0"),
this setting is valid.
In ASK Demodulation (h'0A[D4]FSK_ASK = "1"), input to this register is invalid, because the threshold level is automatically set.
- Setting Range
[D7:D0] = 0 - 255 (b'00000000 - b'11111111)
Initial Value: 61 (b'00111101)
For details, see section 6.5.9.
Notice: In ASK Demodulation (h'0A[D4]FSK_ASK = "1"), the value of that threshold level for automatically setting cannot be
read.
6.10.10 h'12 TX Deviation Setting
D7
Name
Dev5
Initial
0
Type
R/W
[D7:D2]Dev5..0 [Deviation]
This deviation depends on the setting of RF frequency band.
- Setting Range
[D7:D2] = 0 - 63 (b'000000 - 111111)
Initial Value: 12 (b'001100)
- Deviation Setting Range at 30.32MHz Reference Clock Frequency.
315 MHz: Unmodulated, from +/-1.67kHz to +/-105kHz
434 MHz: Unmodulated, from +/-2.5kHz to +/-157.5kHz
868 / 915 MHz: Unmodulated, from +/-5kHz to +/-315kHz
Notice: When to set this register value to "0", RF output signal is unmodulated.
Example)
Deviation: +/-dev = fd × n / nd
fd: Frequency Resolution of VCO 10kHz (= fosc / 3032) * fosc: Reference Clock Frequency (30.32MHz)
nd: Division Ratio (nd = 6 at 315MHz Band, nd = 4 at 434MHz Band nd = 2 at 868 / 915MHz Band)
n: value of register:[D7:D2]Dev5..0 (Converted to decimal)
Notice:
In ASK Receiving / Transmitting and FSK Receiving, settings of register h'12[D7:D2] are invalid.
The change of "fosc" results the change of deviation.
Table 6-64 Register (h'11)
D6
D5
Charge2_
Charge2_
Charge2_
Th6
Th5
0
1
R/W
R/W
Table 6-65 Register (h'12)
D6
D5
Dev4
Dev3
0
1
R/W
R/W
D4
D3
Charge2_
Charge2_
Th4
Th3
Th2
1
1
R/W
R/W
R/W
D4
D3
Dev2
Dev1
Dev0
1
0
R/W
R/W
R/W
64
TC32306FTG
D2
D1
D0
Charge2_
Charge2_
Th1
Th0
1
0
R/W
R/W
D2
D1
D0
NIR_2H1
NIR_2H0
0
0
R/W
R/W
2015-10-01
1
0
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