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[D5]IFBW [IF Filter Bandwidth]
[D5]IFBW
0
1
Change IF Frequency depends on IF Filter Bandwidth.
[D4:D1]BRF_Bit3..0 [Bit Rate Filter Cutoff Frequency]
For details, see Table 6-25.
[D0]
Set to "0" surely.
6.10.7 h'0F RX Function Settings 1
D7
Name
Preamble_
Drssi_en
Initial
0
Type
R/W
[D7]Drssi_en [RSSI Detection]
0: Disable / 1: Enable
[D6]Preamble_en [Preamble Detection]
0: Disable / 1: Enable
[D5]Ndet_en [Noise Detection]
0: Disable / 1: Enable
[D4] Hdet_en [High Frequency Detector]
In Delay Detection (h'10[D0]Sel_Det = "0"), this register setting is valid.
0: Disable / 1: Enable
[D3]Dataout_cnt_en [DATA_IO Control]
0: Disable / 1: Enable
[D2]Digital_en [Digital Block Control]
Digital Block (Detctor, LPF(ASK), LPF(FSK), BRF, Data COMP) Control
0: Disable / 1: Enable
[D1]Det_reset_n [Detection Reset (RSSI Detection / Noise Detection / Preamble Detection)]
0: Detection Reset (Auto resume)
1: Reset is released
Notice:
These detections are reset after writing all the registers in this address.
The function is resumed automatically at the rising edge of CS signal after setting this register.
TC32306FTG always outputs previous input value of the register whichever the auto resume or not,
(If this register is written to "0", the register outputs "0", after that auto resume.)
IF Filter Bandwidth
320kHz
270kHz
Table 6-62 Register (h'0F)
D6
D5
Ndet_en
Hdet_en
en
0
0
R/W
R/W
R/W
62
IF Frequency
230kHz
280kHz
D4
D3
D2
Dataout_
Digital_en
cnt_en
0
0
R/W
R/W
TC32306FTG
D1
D0
Det_reset_n
NIR_L2
1
1
1
R/W
R/W
2015-10-01
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