F2B: A Proc Block Diagram - Panasonic DVCPRO50 Service Manual

F2B: A PROC BLOCK DIAGRAM

IC4500<9>
DIF CNT 1/2
P100 P4001
55
AES
15A 13C AES12_IN Phase
56
Decoder
15B 14A AES34_IN CONV
48KHz_H
P3000 P4001
57
9B 16B S REC_AUD 12
58
9C 16C S REC_AUD 34
AES Phase
Decoder CONV
48KHz_H
P3002 P4001
131
PLL
24A 22C REF_CLK27_AP
IC4400<7>
P4002 P4001
ANALOG IN 12
198 94
24C 24C ADSD 12
200 96 ANALOG IN 34
24B 24B ADSD 34
202 90
26A 26A CUE_MET DATA
PCM_CTL 2/2
FPGA (PLD)
41 34
44 40
P3002 P4001
13C 17B PB DATA 12
14C 18B PB DATA 34
13B 17A PB FS 1 PB FS 1
14B 18A PB FS 2 PB FS 2
15B 19A PB FS 256 PB FS 256
14A 17C PB FRM A1
15A 18C PB FRM A2
18A 28C A PROC_CLK18
18B 22A A PROC_FEND
17A 20C A PROC_CLK27 IC4301<5>
CLK
6
FS256
Converter
(CLK27 FS256)
IC4100<3>
2-9
IN_BUFF
P4001
5C
AV_ADRS[0-10]
2-4 IC4102<3>
2B
BUFF
P4001
6 14
6B
AV_IOWR_L
8 12
6C AV_RST_L
5 14
6A AV_IORD_L
P1 P4001
7 15
20C 2A
AV_CS_APROC_L
IC4101<3>
P4001
2-9
9B
IN_BUFF
AV_DATA[0-7]
7A
P4350
TDO
TDI
TMS
TCK
IC4350<6>
P4001
BUFF
4
11A ISP_TDI
6
11B ISP_TMS
8
11C ISP_TCK
18
12B ISP_TDO
P100 P4001 L :ON
1
28A 12A ISP_SEL2
12C CONF_INFO
19
CONF DONE
IC4601<11>
FPGA (PLD)
131
RecInDatA
130 RecInDatB
Att 203 DIGITAL IN 12 127 RecInDatE
-6dB DIGITAL IN 34 126 RecInDatF
129 RecInDatC
128 RecInDatD
Delay
Att
204
-6dB
INT_SG
FS16M 4
104 PBInDatA
103 PBInDatB
98 CueInDatA
IC4552<7>
34
13 SER IN A SER OUT A
SER IN B SER OUT B
14 35
11
FSA
12
FSB
7
8
142
5
SLOW
6
IC4550,4551
4553,4554
SRAM 4
IP4351<6>
16 13
14 25
12 32 2,7,31
2 28
ROM for FPGA
<<Original>> <<PLAYBACK Signal>>
APC-LSI
REC REC
Meter
Volume SEL
B/C RECOutDatA
RECOutDatB
PBSel
Mute
REC
Delay
PBVolSel
E. E
Moni
Volume
PB
Volume
PB
Delay
MonSel
39
IC4602<11>
SRAM
DATA & CLK
LINE OUT 34
AV_DATA & AV_ADRS etc
130
NCE
83 CONF_DONE
171
Phase
Delay
CONV
Phase
173
Delay
CONV
31
132,133
DATA & CLK
<<REC & EE Signal>>
IC4400<7>
MONIOUT 49
197
CueOutDat 122 CUE MIX REC
PCMCTL
84
CH1/CH2 65
83 66
CH3/CH4
PBOutDatA 82 CH1/CH2 67
delay
PBOutDatB 81 CH3/CH4 68
LPF_EN_H_CH1
LPF_EN_H_CH2
LPF_EN_H_CH3
LPF_EN_H_CH4
77
FS_V
ITS Delay
Phase
CONV
ITS Delay
Phase
CONV
AUD_4CH_H
179
187
27
PB FS 256
35
PB FS 1
36
PB FS 2
FS JOG 12
FS
FS JOG 34
ReGen
185
NCEO
132,133
104 103
F16M OUT
SRC1 OUT
LINE OUT 12
F16M OUT
SRC2 OUT
50 58
FPGA (PLD)
PB L
2/2
REF IN + STD L
Other than above H
Delay AES ENCODER
Delay AES ENCODER
Delay AES ENCODER
AUD_4CH_H
Delay AES ENCODER
Block Sync Gen.
91
92
P4001 P4002
193
DASD LR 24A 24A
P4001 P4002
196
CUE_MIX_DATA
26B 26B
1/2
FPGA (PLD) P4001 P3002
45
REC_DATA_12 21A 17B
46
REC_DATA_34 21B 17C
P4001 P4002
194
DASD_12 23B 23B
195
DASD_34 23B 23C
DV_PB_L
LPF
(3KHz)
AUD_4CH_H
DV_PB_L
DV_PB_L
DV_PB_L
131
IC4651<12>
42
43
SRC
30
IC4652<12>
42
43
SRC
30
IC4500 <9>
DIFCNT
P4001 P3000
46
S_PB_AUD12 15B 10B
P4001 P3000
47
S_PB_AUD34 15C 10C
P4001 P100
48
AES12 OUT 14B 16A
P4001 P100
49
AES34 OUT 14C 16B
P4001 P3002
FS256 19C 16A
P4001 P4002
MCK1 25C 25C