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Standard Event Status Register
The Standard Event Status Register represents eight summary messages, each being defined by a single bit in the
Register. Each bit is given a decimal weighting according to its position in the register.
The Standard Event Status Register can be read using the query *ESR?. The register is read destructively, i.e., its
contents is cleared when read. The register can also be cleared by the command *CLS.
Each summary message represents a specific event that can occur in the analyzer. These summary message bits
have a standardized meaning within IEEE 488.2.
Bit
Event
PON
Power On
User Request
CME
Command
Error
EXE
Execution
Error
DDE
Device
Dependent
Error
Query Error
Request
Control
Operation
Complete
Motorola Communications Analyzer
Programming Reference
Event Status Register Bit Definition
PON - Power On
URQ - User Request
CME - Command
EXE - Execution
DDE - Device Dependent Error
QYE - Query Error
RQC - Request
OPC - Operation Complete
Description
This event bit indicates that an off-to-on transition
has occurred in the analyzer's power supply. This bit
is initially set high when the analyzer is first
powered on.
This event bit indicates the local control "Fl key
press" has occurred.
This event bit indicates (1) an IEEE 488.2 syntax error
has been detected by the parser, (2) a semantic error
occurred indicating an unrecognized header was
or
received,
entered into the Input Buffer inside of a <Program
Message>.
This event bit indicates (1) a <Program Data> element
is evaluated to be out of the range handled by the
analyzer or (2) a valid message could not be executed
due to a condition in the analyzer.
This event bit indicates an error has occurred that is
specific to the analyzer.
This event bit indicates (1) an attempt is made to read
the output queue when no output is present or pending,
or (2) data in the Output Queue has been lost.
This event bit indicates the device is requesting to
become a controller. The analyzer will never assert
this message.
This event bit is generated in response to the *OPC
command when all pending operations have completed.
16
Error
Error
Control
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