Table of Contents
Advertisement
Section 11
Testing functionality by secondary injection
4.
If the test has been performed by injection of current in phase A, repeat the test, injecting current
into phases B and C with polarizing voltage connected to phases B, respectively C (1 out of 3
currents for operation).
5.
If the test has been performed by injection of current in phases AB, repeat the test, injecting current
into phases BC and CA with the appropriate phase angle of injected currents.
6.
Connect a trip output contact to a timer.
7.
Set the injected current to 200% of the trip level of the tested stage, switch on the current and
check the time delay.
For inverse time curves, check the trip time at a current equal to 110% of the trip current for txMin.
8.
Check that all trip and pickup contacts trip according to the configuration (signal matrixes).
9.
Reverse the direction of the injected current and check that the protection does not trip.
10.
If 2 out of 3 or 3 out of 3 currents are chosen for operation: Check that the function will not trip with
current in one phase only.
11.
Repeat the above described tests for the higher set stages.
12.
Check that pickup and trip information is stored in the event menu .
11.4.1.3
Completing the test
Continue to test another function or end the test by changing the TESTMODE setting to Disabled.
Restore connections and settings to the original values, if changed for testing purposes.
11.4.2
Four step residual overcurrent protection, (Zero sequence or
negative sequence directionality) EF4PTOC (51N/67N)
Prepare the IED for verification of settings outlined in Section
Values of the logical signals for D2PTOC are available on the local HMI under Main menu/Test/
Function status /Current protection/ResidualOverCurr4Step(51N_67N,4(IN>)) /
EF4PTOC(51N_67N;4(IN>)):x, where x = instance number.
The Signal Monitoring in PCM600 shows the same signals that are available on the local HMI.
11.4.2.1
Function revision history
Document
revision
A
B
C
D
E
F
G
H
J
108
Product
History
revision
2.2.1
-
2.2.1
-
2.2.2
Technical data table updated with note "Operate time and reset time are only valid if
harmonic blocking is turned off for a step".
2.2.3
-
2.2.3
-
2.2.4
-
2.2.4
-
2.2.4
The phase selection logic is added to allow phase segregated trip. The new phase
selections outputs added to this release are PHSELL1, PHSELL2 and PHSELL3. The setting
EnPhaseSel is added to enable or disable phase selection. The maximum value changed to
2000.0 % of IBase for IMin1, IMin2, IMin3 and IMin4 settings.
2.2.5
The harmonic restrain function changed to freeze the definite and IDMT timers.
© 2017 - 2022 Hitachi Energy. All rights reserved
1MRK 511 409-UUS Rev. K
"Preparing the IED to verify
GUID-0F9199B0-3F86-45E0-AFC2-747052A20AE1 v2
Phasor measurement unit RES670
Commissioning manual
SEMOD56287-118 v4
SEMOD53296-3 v10
settings".
Advertisement
Table of Contents
