Hitachi Relion RES670 Commissioning Manual page 95

Phasor measurement unit
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1MRK 511 409-UUS Rev. K
1.
Create a test sequence such that the power swing should be detected . This can be done by
referring to steps 5, 6, and 7 described in section
ZMBURPSB
three phases. With this condition, the output signal START will be activated.
2.
After expiration of the set time delay by a timer tR2, the output START will disappear.
3.
If required to block inhibit of start output by the presence of slow power swings, BLKI01 must be
configured to TRUE. Thereby, the output signal START will be maintained as long as the power
swing condition exists.
Inhibit START output by the single pole reclosing
Preconditions
The input signal I0CHECK, residual current (3I0) detection used to inhibit the start output, must be
configured to the output signal STPE on the FDPSPDIS, FRPSPDIS, ZMFPDIS or ZMFCPDIS function.
The input signal BLKI02, block inhibit of the start output for subsequent residual current detection and
BLKI01, block inhibit of the start output for slow power swings must be connected to TRUE.
1.
Create a phase-to-earth fault such that the input signal I0CHECK will be activated and a trip signal
from any impedance protection function will be generated.
2.
With this condition, the input signal TRSP connected to a tripping function is activated.
3.
Clear the fault by injecting zero current magnitude in the fault phase and maintain healthy
conditions in other phases. With this, I0CHECK and TRSP will be deactivated.
4.
Make a test sequence to create power swing condition in healthy phases in accordance with steps
5, 6, and 7 described in section
condition, the output signal START will be activated.
5.
Repeat step
6.
Steps
two phase power swing during single pole autoreclosing time and then switched-on-to the
persistent phase-to-earth fault after single pole autoreclosing time.
7.
By doing this, the output signal START will be inhibited.
8.
If I0CHECK appears the expiration of a timer tEF, the condition will be seen as power swing and
thereby, the output signal START will be maintained as long as the power swing exists in the power
system.
Testing the power swing unblocking logic
Preconditions
The following output signals shall be configured to binary outputs: FLTL1, FLTL2, FLTL3, FLT1PH,
FLT2PH, FLT3PH and START.
Ensure that the setting OpModePSU is set to On.
1.
Inject rated currents and voltages in all three phases. The service values IL1, IL2, IL3 and UL1,
UL2, UL3 can be monitored in the local HMI.
2.
Create a test sequence such that power swing has been detected, which can be done by referring
to steps 5, 6 and 7 described in section
inject voltage in one of the phases accordingly by keeping constant current in all three phases. With
this condition, the output signal START will be activated.
3.
Create a phase-earth fault condition by simultaneously reducing the voltage and increasing the
current in phase L1. Ensure that the residual current (3I0) is above 20% IB and the negative
sequence current (I2) is above 12% IB. At this condition, the outputs FLTL1 and FLT1PH will be
activated. The service values STCND and RELCND will show the value as 1.
Phasor measurement unit RES670
Commissioning manual
and inject voltage in one of the phases accordingly by keeping constant current in all
1
to create phase-to-earth fault and thereby, I0CHECK will be activated again.
4
and
5
must be performed before the expiration of set time delay of tEF. There may exist a
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Testing the power swing detection logic
Testing the power swing detection logic ZMBURPSB
Testing the power swing detection logic ZMBURPSB
Section 11
Testing functionality by secondary injection
GUID-B7B8DBCE-9945-4C1A-8319-96920DC31DCA v1
(68). With this
GUID-1B635221-493D-4DB3-938C-6C61461E3B16 v1
and
89

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