HP 10343B Operating Manual page 74

Reset and Bus Free. When the SCSI Bus is in the Bus Free State and
Reset is true, a clock pulse is generated. The D Flip-Flop U18 is put into
the reset state when the bus goes free. The reset line is inverted by U10D
and is low true ANDed into the OR Gate U7A with the low true Q output
of U18. This condition causes a 25 ns pulse at the output of U9C by
delaying one of its inputs with the delay line U16 and the inverter U10B.
The delay line U8A delays the clock to provide enough setup time for the
information-transfer bit into the logic analyzer inputs.
If the SCSI Bus is in the Bus Free State and Reset becomes enabled, all of
the lines on the SCSI Bus are latched into the logic analyzer 45
nanoseconds after Reset became active.
Reset is captured by the logic analyzer if it is asserted before an analyzer
clock. Otherwise, an extra analyzer dock is generated when the bus goes
into the Bus Free phase. The logic analyzer will print "Reset Bus Free" for
that state.
All of the lines on the SCSI Bus are latched into the logic analyzer 450
nanoseconds after both Busy and Select become released if Reset is also
true at that same time. If Reset is not true, no logic analyzer clock is
generated while entering the Bus Free State.
The information-transfer bit (INF) is generated inside of the HP 10343B
to differentiate between the Arbitration phase and the Data Out phase on
the Status lines. The Busy line is not sent to the logic analyzer state input
since it is not required to decode the SCSI phases with the INF bit
available.
INF is accomplished with the D Flip-Flop U18. This flip-flop is set when
the bus goes into its information phases after the Select or Reselect phase.
This always occurs when Select is high in the D input and is stored by Busy
going high at the end of the Select or Reselect phase. The logic analyzer
does not see this as a info-xfer phase because this happens at the end of
the phase and the analyzer is clocked at the beginning of the phase.
Additional Information
A-13