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The bus is out of the information-transfer (INF) phases when it returns to
a Bus Free State. The bus is free when Busy and Select are false for a
period of 400nS. U18 is reset at this time through the OR Gates U7B and
C, and the 400nS delay line U8B.
All of the conditions that can cause a logic analyzer clock must be output
on one line. This is accomplished by AND mg them together with the
AND Gates U9A and U9B.
Note
Some states may not capture the A TN signal. In an information
output phase where the initiator is sending information, the HP
10343B generates the logic analyzer clock on the asserted edge of
Acknowledge. If ATN is true when Request becomes asserted,
butATN goes false before Acknowledge is asserted, ATN may
not be captured as true in that state.
Testing and
There are no established field testing procedures for the HP 10343B. The
TrOU bleshOOti no
10343B is part of the Board Exchange Program. This program allows
9
you to exchange a faulty assembly with one that has been repaired,
calibrated, and performance verified by the factory. If your instrument is
inoperative, contact the nearest Hewlett-Packard Sales and Service Office
for assistance.
Replaceable
Parts
Since the HP 10343B is part of the Board Exchange Program, the only
replaceable parts are the major parts and cabling. These are listed in
table A-l. Hie component level parts shown in table A-l are for
reference purposes only. Figure A-5 shows an exploded view of the
HP 10343B.
Additional Information
A-14
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