Testing Up To 1.3 Gbit/S With Two 660 Mbit/S Outputs - HP 81200 User Manual

Timing Principles
HP 81200 Data Generator/Analyzer Platform User Guide, Revision 2.1
If the frequency multiply factor is changed for individual ports or
terminals, then the blocklength granularity, memory depth and frequency
also change for this connector.
If you multiplied the system frequency at a certain data port by 2, then the
blocklength granularity for this connector would become 16, the memory
depth would be 1 Mbit, and the data rate for this port would be 400 Mbit/s.
This general rule may be restricted by the designated frontend(s), because
some generator or analyzer frontends are restricted to a range of 200 or
330 MHz, respectively.
Testing up to 1.3 Gbit/s with Two 660 Mbit/s
Outputs
Two 660 Mbit/s outputs in RZ mode, 50 % duty cycle and the second output
delayed with 50 % of the period can be added to achieve a 1.3 Gbit/s NRZ
data stream.
Channel Addition
Two or four channels can be digitally added. The digital channel addition is
an XOR addition (exclusive OR or modulo 2 addition). The addition takes
place before levels are applied to the signals.
Channel 1
Channel 2
Digital Addition (XOR)
of Channel 1 and
Channel 2
Figure 7 Channel Addition
Introduction to the System
Digital Addition (XOR)
33