Motorola MOSCAD 68P02958C00-B User Manual page 312

18. The number of empty frames ready to be received.
19. The number of frames received.
20. The number of frames transmitted.
21. The number of empty frames directed to transmission.
## 261 LEVEL = 1
HDLC hardware control and status :-
Internal software data (key)
Internal hardware registers
Internal hardware parameters
Scc configuration register
Scc mode register
Scc data sync. register
Scc event register
Scc mask register
Scc status register
Temp receive crc
Crc polynom mask
Temp transmit crc
Discard frame counter
Crc error counter
Abort sequence counter
Nonmatch address counter
Frame retransmit counter
Receive frame maximum length
Receive frame length counter
User define frame address mask
User define frame addresses (HADDRX)
1. Device key address.
2. Address of H-W registers.
3. Address of H-W parameters.
4. Determines the clock direction (Rx or Tx) and the baud rate
5. Determines the work mode — HDLC or UART.
6. Determines the HDLC flags.
7. The events that generate the interrupt.
8. Mask to block the interrupt.
9. The CM (Channel Monitor) and TD (Tone Detect) statuses.
10. Not in use.
11. Mask of received addresses.
12. The addresses to which this site responds via this port.
(DATA)
(IREG)
(IRAM)
(SCON)
(SCM)
(DSR)
(SCCE)
(SCCM)
(SCCS)
(RCRC_L/H)
(C_MASK_L/H)
(TCRC_L/H)
(DISFC)
(CRCEC)
(ABTSC)
(NMARC)
(RETRC)
(MFLR)
(MAX_CNT)
(HMASK)
C-20
Software Diagnostics Output
: %% 1
: %% 2
: %% 3
: %% 4
: %% 5
: %% 6
: %% 7
: %% 8
: %% 9
: %% %% 10
: %% %% 10
: %% %% 10
: %% 10
: %% 10
: %% 10
: %% 10
: %% 10
: %% 10
: %% 10
: %% 11
: %% %% %% %% 12