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Processor PCB
Table 2-1 Card Cage Socket Contact Assignments (cont'd)
PIN
READ/
NUMBER
NAME
WRITE
DESCRIPTION
R27
DT/R
W
Data Transmit or Receive. This line indicates
data transfer direction. When High, direction
is processor to 110 or memory; when Low,
direction is 110 or memory to processor.
L27
CLKO
W
Communication Clock. This line, which is
energized by the 8253-5 Programmable Inter-
val Timer, conveys a synchronizing variable
frequency clock to the communications
control.
R30
AO
W
Address Bit O. When this line is active (High),
the memory or 110 device associated with the
least significant half of the data is enabled to
read or transmit its data.
R31, L30
Al to A7
W
Address Bits 1 Through 7. These seven lines
R32, L31
address the memory or 110 device. These
R33, L32
signals are latched.
L33
R34, L34
ADO to
W
Address and Data Lines 0 Through 15. These
R35, L35
AD15
16 lines are bidirectional and time multi-
R36, L36
plexed to convey address or data to the
R37, L37
address or data buses.
R38, L38
R39, L39
R40, L40
R4I, L41
R42, L42
Al6 to
W
Address Lines 16 Through 19. These four lines,
R43,L43
AI9
used for addressing the memory, increase the
number of address lines to twenty, allowing
access to one megabyte of memory.
2-7
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