NEC Advanced Personal Computer System Reference Manual page 25

Processor PCB
Table 2-1 Card Cage Socket Contact Assignments (cont'd)
PIN
NUMBER NAME
R23 lOR
L23 DMC
R24 MRQ
L24 MR
R25 RFSH
L25 MW
R26 BHE
L26 ALE
2-6
READ/
WRITE DESCRIPTION
W IIO Read. A Low on this line instructs the
110 device to transmit its data to the data bus.
This instruction can come from either the
DMA controller or the processor.
W DMA Cycle. A High on this line indicates the
processor has been inhibited, thus giving
system-bus control to the DMA controller.
W Memory Request. When this line is Low, it
indicates the memory cycle is in operation.
The line is inactive (High) during memory-
refresh cycles.
W
Memory Read. This line instructs the addi-
tional memory to transmit its data onto the
data bus. Either the processor or DMA con-
troller can activate this signal, which is active
Low.
W Memory Refresh. When this line
IS
Low,
dynamic memory is refreshed.
W Memory Write. When Low, this line instructs
the selected memory to receive the data on the
data bus. It is activated by either the DMA
controller or processor.
W Bus High Enable. When Low, this line indi-
cates that the most significant half of the data
line is ready to be read. This line is not used
during DMA cycles.
W Address Latch Enable. When activated by the
processor or DMA control, the signal on this
line latches the address on the bus.