Main Memory; Main Memory Block Diagram - NEC Advanced Personal Computer System Reference Manual

2.6.1 Main Memory
The Processor PCB contains 128 KB (64 K words: 16 bits of data, 18 bits wide, with 1
bit parity for each 8 bits)' of RAM, organized into eighteen 64K x I-bit dynamic
memory chips. Figure 2-18 is a block diagram of the circuit. The RAM is refreshed
during the non-memory-access cycle, and its access time is 200 ns. Parity check is
carried out with two additional memory chips. A detected parity error lights the D4
red Light Emitting Diode (LED), located near the top edge of the Processor PCB.
As shown in Figure 2-17, the main memory is expandable to a maximum of 640 KB,
of which 256 KB can be supported by the present APC equipment configuration.
ADDRESSES
1 TO 16
REFRESH ADDRESS
CLOCK
MRQ
MW
AO
BHE
REFRESH
ADDRESS
\
CONNECTOR
t
REFRESH
TIMER
REFRESH
REQUEST
REFRESH
ARBITER
Figure 2-18 Main Memory Block Diagram
ADDRESS
MUX.
DATA
8 TO 15
DATA
o
TO 7
REFRESH
READY
CONTROL
RAS
MEMORY
CAS
CONTROL
LOGIC
WR
MEMORY
(HIGH)
MEMORY
(LOW)
-
64K X 9
Processor PCB
DATA
8 TO 15
DATA
o
TO 7
RDY
2-27