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Table 2-1 Card Cage Socket Contact Assignments (cont'd)
PIN
NUMBER
NAME
R20
TC
R21
PHIO
L21
IRST
R22
lOW
L22
RDY
READI
WRITE
DESCRIPTION
W
Terminal Count. This line carries to the 110
device a one-clock-duration pulse indicating
that the terminal count for the DMA channel
has been reached. This pulse is active High.
W
System Clock. The pulse of the clock is
transmitted on this line; the clock period is
about 200 nsec (4.9152 MHz) and its duty
cycle is 33 percent.
W
Initial Reset. When this line goes High, every
device in the system is initialized. This line is
activated at power on.
W
110 Write. A Low on this line instructs the
110 device to receive data from the data bus.
Either the DMA controller or processor can
activate the line.
R
Ready. A High on this line indicates that data
has been received by an 110 device or
memory, or that preparation of data is com-
plete. It is pulled Low by a device to lengthen
110 memory cycles, allowing slower devices
to adjust to the 110 channel.
NOTE
There is an Interval-Ready signal
within the G9PFBU PCB; it acti-
vates when memory access from
the processor or DMA controller
clashes with the memory-refresh
cycle.
Processor PCB
2-5
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