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Figure 8-11. Format of Data/Handshake Packet Receive Mode Register
Symbol
7
6
URXMOD
0
0
RESMOD
0
Reject USB reset signal less than 3.0 s SE0 (Single-ended 0) period.
1
Detect transition from J state to SE0 as USB reset signal.
DINTEN
0
Do not generate data packet receive status synchronous interrupt.
1
Generate data packet receive status synchronous interrupt
DWRMSK
0
Enable write operation to all addresses in data/handshake packet receive buffer.
1
Disable write operation to addresses greater than 11H in data/handshake packet receive buffer.
Notes 1. Because this is the flag used to detect a USB reset in bus suspend mode, do not set data in bus
idle mode.
immediately when returning from the bus suspend mode.
2. If the bus is disturbed by noise, the noise is detected as a USB reset signal. Confirm whether the
USB reset signal has been input by checking the URESRX flag (bit 4 of the USB receive status
register (RXSTAT)) more than once by software.
3. The receive status synchronous interrupt occurs at the following timing during data/handshake
packet receive interrupt (INTUSBRD) signal input.
Sync
INTUSBRD
(DINTEN = 0)
INTUSBRD
(DINTEN = 1)
110
CHAPTER 8
USB FUNCTION
5
4
3
0
0
0
RESMOD DINTEN DWRMSK
USB reset signal detection mode setting
µ
Data packet receive status synchronous interrupt enable flag
Data/handshake packet write disable setting
And do not set data immediately before entering bus suspend mode.
Data0
Data1
DataX
Packet ID detected
Data packet
receive status
synchronous interrupt
User's Manual U12978EJ3V0UD
<2>
<1>
<0>
Address
Note 2
Note 3
.
CRC16
Data/handshake packet
receive interrupt
After reset
R/W
FF66H
00H
R/W
Note 1
Clear
EOP
EOP received
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