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Mnemonic
Operands
CALL
!addr16
CALLT
[addr5]
RET
RETI
PUSH
PSW
rp
POP
PSW
rp
MOVW
SP, AX
AX, SP
BR
!addr16
$addr16
AX
BC
$saddr16
BNC
$saddr16
BZ
$saddr16
BNZ
$saddr16
BT
saddr.bit,$addr16
sfr.bit,$addr16
A.bit,$addr16
PSW.bit,$addr16
BF
saddr.bit,$addr16
sfr.bit,$addr16
A.bit,$addr16
PSW.bit,$addr16
DBNZ
B,$addr16
C,$addr16
saddr,$addr16
NOP
EI
DI
HALT
STOP
Remark One instruction clock cycle is one CPU clock cycle (f
register (PCC).
206
CHAPTER 15
INSTRUCTION SET
Bytes
Clocks
(SP−1) ← (PC+3)
3
6
PC ← addr16, SP ← SP−2
(SP−1) ← (PC+1)
1
8
← (00000000, addr5+1),
PC
H
← (00000000, addr5), SP ← SP−2
PC
L
← (SP+1), PC
1
6
PC
H
← (SP+1), PC
1
8
PC
H
PSW ← (SP+2), SP ← SP+3, NMIS ← 0
(SP−1) ← PSW, SP ← SP−1
1
2
(SP−1) ← rp
1
4
PSW ← (SP), SP ← SP+1
1
4
← (SP+1), rp
1
6
rp
H
SP ← AX
2
8
AX ← SP
2
6
PC ← addr16
3
6
PC ← PC+2+jdisp8
2
6
← A, PC
1
6
PC
H
PC ← PC+2+jdisp8 if CY=1
2
6
PC ← PC+2+jdisp8 if CY=0
2
6
PC ← PC+2+jdisp8 if Z=1
2
6
PC ← PC+2+jdisp8 if Z=0
2
6
PC ← PC+4+jdisp8 if (saddr.bit)=1
4
10
PC ← PC+4+jdisp8 if sfr.bit=1
4
10
PC ← PC+3+jdisp8 if A.bit=1
3
8
PC ← PC+4+jdisp8 if PSW.bit=1
4
10
PC ← PC+4+jdisp8 if (saddr.bit)=0
4
10
PC ← PC+4+jdisp8 if sfr.bit=0
4
10
PC ← PC+3+jdisp8 if A.bit=0
3
8
PC ← PC+4+jdisp8 if PSW.bit=0
4
10
B ← B−1, then PC ← PC+2+jdisp8 if B≠0
2
6
C ← C−1, then PC ← PC+2+jdisp8 if C≠0
2
6
(saddr) ← (saddr)−1, then
3
8
PC ← PC+3+jdisp8 if (saddr)≠0
1
2
No Operation
IE ← 1 (Enable interrupt)
3
6
IE ← 0 (Disable interrupt)
3
6
1
2
Set HALT mode
1
2
Set STOP mode
User's Manual U12978EJ3V0UD
Operation
, (SP−2) ← (PC+3)
,
H
L
, (SP−2) ← (PC+1)
,
H
L
← (SP), SP ← SP+2
L
← (SP),
L
, (SP−2) ← rp
, SP ← SP−2
H
L
← (SP), SP ← SP+2
L
← X
L
) selected by the processor clock control
CPU
Flag
Z AC CY
R R R
R R R
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