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(b) 3-wire serial I/O mode (T
(i) SCK10 ...Internal clock output (when f
Parameter
SCK10 cycle time
SCK10 high-/low-level width
SI10 setup time
SI10 hold time
SO10 output delay
Notes 1. Bit 4 of serial operation mode register 10 (CSIM10)
2. CL is the capacitance of the SO output line.
(ii) SCK10 ...External clock output
Parameter
SCK10 cycle time
SCK10 high-/low-level width
SI10 setup time
SI10 hold time
SO10 output delay
Note CL is the capacitance of the SO output line.
CHAPTER 16
ELECTRICAL SPECIFICATIONS
= − − − − 40 to +85° ° ° ° C, V
A
DD
= 6.0 MHz)
X
Symbol
Conditions
Note 1
t
When TPS100
= 0
KCY1
Note 1
When TPS100
= 1
Note 1
t
,
When TPS100
= 0
KH1
t
KL1
Note 1
When TPS100
= 1
To SCK10 ↑
t
SIK1
From SCK10 ↑
t
KSI1
From SCK10 ↓, CL = 100 pF
t
KSO1
Symbol
Conditions
t
KCY2
t
,
KH2
t
KL2
t
SIK2
t
KSI2
From SCK10 ↓, CL = 100 pF
t
KSO2
User's Manual U12978EJ3V0UD
= 4.0 to 5.5 V)
MIN.
667
1,333
283
617
150
Note 1
When TPS100
= 0
333
Note 1
When TPS100
= 1
667
Note 2
MIN.
667
283
100
333
Note
TYP.
MAX.
Unit
667
667
ns
1,333
1,333
ns
333
ns
667
ns
ns
ns
ns
0
200
ns
TYP.
MAX.
Unit
ns
ns
ns
ns
0
250
ns
215
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