NEC switch User Manual page 205

Mnemonic Operands
CMP A,#byte
saddr,#byte
A,r
A,saddr
A,!addr16
A,[HL]
A,[HL+byte]
ADDW AX,#word
SUBW AX,#word
CMPW AX,#word
INC r
saddr
DEC r
saddr
INCW rp
DECW rp
ROR A,1
ROL A,1
RORC A,1
ROLC A,1
SET1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CLR1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
SET1 CY
CLR1 CY
NOT1 CY
Remark One instruction clock cycle is one CPU clock cycle (f
register (PCC).
CHAPTER 15 INSTRUCTION SET
Bytes Clocks
2 4 A−byte
3 6 (saddr)−byte
2 4 A−r
2 4 A−(saddr)
3 8 A−(addr16)
1 6 A−(HL)
2 6 A−(HL+byte)
AX,CY ← AX+word
3 6
AX,CY ← AX−word
3 6
3 6 AX−word
r ← r+1
2 4
(saddr) ← (saddr)+1
2 4
r ← r−1
2 4
(saddr) ← (saddr)−1
2 4
rp ← rp+1
1 4
rp ← rp−1
1 4
1 2 (CY,A
7
1 2 (CY,A
0
(CY ← A
1 2
(CY ← A
1 2
(saddr.bit) ← 1
3 6
sfr.bit ← 1
3 6
A.bit ← 1
2 4
PSW.bit ← 1
3 6
(HL).bit ← 1
2 10
(saddr.bit) ← 0
3 6
sfr.bit ← 0
3 6
A.bit ← 0
2 4
PSW.bit ← 0
3 6
(HL).bit ← 0
2 10
CY ← 1
1 2
CY ← 0
1 2
CY ← CY
1 2
User's Manual U12978EJ3V0UD
Operation
← A ← A
, A )×1
0 m−1 m
← A ← A
, A )×1
7 m+1 m
← CY, A ← A
, A )×1
0 7 m−1 m
← CY, A ← A
, A )×1
7 0 m+1 m
) selected by the processor clock control
CPU
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× ×
× ×
× ×
× ×
×
×
×
×
× × ×
× × ×
1
0
×
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