Sync Detection/Usbclk Detector Operation; Timing Of Sync Detection/Usbclk Detector Operation; Timing Of Sync Detection/Usbclk Generation Operation - NEC switch User Manual

8.8.3 Sync detection/USBCLK detector operation

This circuit generates the USBCLK signal (1.5 MHz) upon detecting the sync part of the receive packet. In
addition, it contains an NRZI decoder that decodes receive packets and detects the last bit of the sync part.
When the last sync bit is detected, a signal that specifies start of storing in the ID detection buffer is output.
Figure 8-27. Timing of Sync Detection/USBCLK Detector Operation
Receive packet
USBCLK
Data after decoding
Figure 8-28. Timing of Sync Detection/USBCLK Generation Operation
f
X
Note
TX MASTER EN
L
USBCLK
Receive data
(RXD)
Note
Resume RX
(INTUSBRE)
Note Because these signals are used internally, confirmation by software is not possible.
Remark The USB clock starts operating at the falling edge of f
the bus. However, this control is masked if TX MASTER EN = 1.
148
CHAPTER 8 USB FUNCTION
USBCLK generation
NRZI decode
SYNC pattern
0 1 0
Idle Sync
User's Manual U12978EJ3V0UD
SYNC last bit detection
After token packet
1 0 1 0 1
after transition from the J state to the K state of
X
1 1 0