Mitsubishi Electric MELSEC iQ-R Series User Manual page 185

■CPU module STOP transition message (Un\G8450 to Un\G8477)
The RJ71CN91 can define up to four transmit messages to send them when the CPU module state changes from RUN to
STOP.
CPU module STOP transition messages 1 to 4 are sent when the CPU module state changes from RUN to STOP.
Best practice is to use only one CPU module STOP transition message. This increases the chances of
sending the message when the CPU module state changes from RUN to STOP. If multiple messages are
defined, they are sent in the order of "CPU module STOP transition message" 1 to 4.
Address Description
Un\G8450 CAN-ID 1 LW
Un\G8451 CAN-ID 1 HW
*2
Un\G8452 DLC
Un\G8453 Data bytes
Un\G8454
Un\G8455
Un\G8456
 
Un\G8471 CAN-ID 4 LW
Un\G8472 CAN-ID 4 HW
*2
Un\G8473 DLC
Un\G8474 Data bytes
Un\G8475
Un\G8476
Un\G8477
*1 Initial value when the CPU module is powered off and on or reset
*2 DLC is an abbreviation of Data Length Count.
The following describes settings of each buffer memory area.
Buffer memory area
CAN ID n (CAN-ID n LW, CAN-ID n HW)
DLC
Data bytes
*3 01H (Send RTR frame) is not available.
Change these settings during offline mode. When the RJ71CN91 transitions to the online mode, the settings
are enabled.
11-bit/29-bit CAN-ID (low word)
11-bit/29-bit CAN-ID (high word)
Data length count
Lower byte Data byte 1
Upper byte Data byte 2
Lower byte Data byte 3
Upper byte Data byte 4
Lower byte Data byte 5
Upper byte Data byte 6
Lower byte Data byte 7
Upper byte Data byte 8

11-bit/29-bit CAN-ID (low word)
11-bit/29-bit CAN-ID (high word)
Data length count
Lower byte Data byte 1
Upper byte Data byte 2
Lower byte Data byte 3
Upper byte Data byte 4
Lower byte Data byte 5
Upper byte Data byte 6
Lower byte Data byte 7
Upper byte Data byte 8
Description
Set the CAN-ID of the message.
To disable the message, set CAN-ID n LW and CAN-ID n HW to FFFFH.
Lower byte: Set the number of data bytes to transmit (0 to 8).
Upper byte: Set to 00H (Send data frame).
Set data to transmit.
CPU module STOP transition
message 1

CPU module STOP transition
message 4
*3
Appendix 2 Buffer Memory
*1
Initial value
FFFFH
FFFFH
0000H
0000H
0000H
0000H
0000H

FFFFH
FFFFH
0000H
0000H
A
0000H
0000H
0000H
APPX
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