Mitsubishi Electric Melsec iQ-R Series User Manual page 126

HART device information refresh completed
The refresh status of the HART device information can be checked.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0
(2)
(1) 0: Refresh uncompleted, 1: Refresh completed
(2) b8 to b15 are fixed to 0.
When the bit corresponding to 'HART device information refresh request' (Un\G2031) is set to Refresh request made (1), and
the HART device information of the target channel is refreshed, Refresh completed (1) is stored in the bit corresponding to
this area. When the bit corresponding to 'HART device information refresh request' (Un\G2031) is set to No refresh request
(0), Refresh uncompleted (0) is stored in the bit corresponding to this area.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART device information refresh completed
HART communication enable/disable setting
Set whether to enable or disable the HART communication for each channel.
For details on the HART communication function, refer to the following.
Page 17 HART Communication Function
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0
(2)
(1) 0: Disable, 1: Enable
(2) b8 to b15 are fixed to 0.
• The HART communication of a target channel is enabled by setting the bit corresponding to the channel to Enable (1). The
enable/disable status of the HART communication of each channel can be checked in 'HART communication enable/
disable setting monitor' (Un\G2075).
• Setting channels where the HART communication is unused to Disable (0) shortens the HART cycle time.
• When a current outside the range of 4 to 20mA is input to channels where the HART communication is used, the HART
communication may not be properly executed.
• The setting of this area is not affected by the setting details of 'CH1 A/D conversion enable/disable setting' (Un\G500). The
setting of this area is enabled even when the A/D conversion is disabled. To use 'CH1 Digital output value' (Un\G400) or
'CH1 Digital operation value' (Un\G402) for the control during the HART communication, set 'CH1 A/D conversion enable/
disable setting' (Un\G500) to A/D conversion enable (0).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART communication enable/disable setting
■Enabling the setting
As soon as a setting value is input, the setting is enabled. Turning on and off 'Operating condition setting request' (Y9) is not
required.
■Default value
The default value is Disable (0) for all channels.
APPX
124
Appendix 3 Buffer Memory Areas
b8 b7 b6 b5 b4
0 0 0 CH8 CH7 CH6 CH5
CH1
2032
b8 b7 b6 b5 b4
0 0 0 CH8 CH7 CH6 CH5
CH1
2074
b3 b2 b1 b0
CH4 CH3 CH2 CH1
(1)
CH2 CH3 CH4
b3 b2 b1 b0
CH4 CH3 CH2 CH1
(1)
CH2 CH3 CH4
CH5 CH6 CH7
CH5 CH6 CH7
CH8
CH8