Mitsubishi Electric Melsec iQ-R Series User Manual page 24

HART cycle time
HART cycle time is the total time required to access each channel where the HART communication is enabled. Refreshing of
each channel is processed in order. Because of this, the HART cycle time differs depending on the number of channels where
the HART communication is enabled.
Ex.
When the HART communication is enabled in all channels, the HART cycle time is as follows.
CH1 CH2
Refresh Refresh
processing processing
■Checking the HART cycle time
The HART cycle time during the HART communication can be checked in the following buffer memory areas.
Buffer memory area
'HART current cycle time' (Un\G2077)
'HART maximum cycle time' (Un\G2078)
'HART minimum cycle time' (Un\G2079)
To reset 'HART maximum cycle time' (Un\G2078) and 'HART minimum cycle time' (Un\G2079), turn off and on 'HART cycle
time maximum value/minimum value reset request' (Y2). The values are reset to the value of 'HART current cycle time'
(Un\G2077). When the reset is completed, 'HART cycle time maximum value/minimum value reset completed flag' (X2) turns
off and on.
Diagnostics of the HART-enabled device
The HART device status information is sent to the A/D converter module every HART cycle time during the HART
communication. The status information includes status of HART device variables and that of output current. The status
information can be checked and the HART-enabled device can be diagnosed in the following buffer memory areas.
Buffer memory area
'CH1 HART field device status' (Un\G2080)
'CH1 HART extended field device status' (Un\G2081)
'CH1 HART device variable status primary value (PV), secondary value (SV)'
(Un\G2082)
'CH1 HART device variable status tertiary value (TV), quaternary value (QV)'
(Un\G2083)
1 FUNCTIONS
22
1.3 HART Communication Function
HART cycle time
CH3 CH4 CH5
Refresh Refresh Refresh
processing processing processing
Description
The current HART cycle time is stored in increments of 10ms.
The maximum HART cycle time is stored in increments of
10ms.
The minimum HART cycle time is stored in increments of
10ms.
CH6 CH7 CH8
Refresh Refresh Refresh
processing processing processing
Details
Page 127 CH1 HART field device status
Page 128 CH1 HART extended field device status
Page 129 CH1 HART device variable status
CH1
Refresh
processing
Refreshing cycle
Updated every time the HART cycle time
elapses.