Sony CXD5602 User Manual page 216

3.7.3 I2C2
The I2C2 is the I2C master and supports Standard and Fast Mode.
3.7.3.1 Register List
Table I2C-81 shows a register list of the I2C2.
Address Register Name
0x041AA000 I2C2 register (For details, refer to the API)
|
0x041AAFFF
3.7.3.2 Clock and Reset
Figure I2C-40 shows the clock and reset system of the I2C2.
When accessing the I2C2 register, supply the clock to the AHB/APB Bus Bridge.
RTC_CLK_IN
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
SYSIOP_SUB_CKEN.I2CM_SUB
SYSIOP_SUB_CKEN.COM_BRG
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_BRG_COMIF
Table I2C-73 I2C2 Register List
Type Description
RCOSC
0
ck_rf_pll_1
1
ck_cpu_bus
2
XOSC
3 1/M
0
1
2
3
0
1
CKDIV_COM.CK_COM
1/M
Figure I2C-40 I2C2 Clock and Reset System
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ck_co m_gear
ck_ahb_gear
1/M
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
SWRESET_BUS.XRST_I2CM_SUB
CXD5602 User Manual
initial
Value
-
I2C2
CK
I2CCLK
GATE
PCLK
PRESETn
AHB/APB
CK
GATE
BusBridge
CK
GATE