Sony CXD5602 User Manual page 227

3.8.4.3.2 Clock Supply Stop
Perform the following control to stop supplying the HCLK clock of the HDMAC.
1. Clock supply stop
SYSIOP_CKEN.AHB_DMAC1=1'b0
3.8.5 SYDMAC
3.8.5.1 Register List
Table DMAC-87 shows the registers that control the SYDMAC.
Address Register Name
0x04122000 PrimeCell
|
0x04122FFC
3.8.5.2 Clock and Reset
Figure DMAC-46 shows the clock and reset system diagram of the SYDMAC.
Reset of the SYDMAC is automatically released when the PWD_SYSIOP power domain is turned ON.
RTC_CLK_IN
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_CKEN.AHB_DMAC2
Table DMAC-79 SYDMAC Control Register List
Type Description
®
Single Master DMA Controller (PL081)
RCOSC
ck_cpu_bus
0
1
ck_rf_pll_1
1/M
2
XOSC
3
0
1
2
3
0
1
Figure DMAC-46 SYDMAC Clock and Reset System
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register
ck_ahb_gear
1/M
Auto(PWD_SYSIOP Power Domain ON)
CXD5602 User Manual
initial
Value
-
SYDMAC
CK
HCLK
GATE
HRESETn