Sony CXD5602 User Manual page 325

I2C1_ACCESS_INH
2
IBIT_REQ
I2C0_ACCESS_INH
1
IBIT_REQ
SPI_ACCESS_INHI
0
BIT_REQ
When the CPU directly accesses I2C1, "1" is set on this bit.
SEQ_CTRL holds the access to I2C1 while the bit is "1".
RW 0x0 Note that if this bit is set "1" for longer time than the
sequencer's access cycle using I2C1 from SEQ_CTRL, the
bit of EXE_ERR_STT will become "1".
When the CPU directly accesses I2C0, "1" is set on this bit.
SEQ_CTRL holds the access to I2C0 while the bit is "1".
RW 0x0 Note that if this bit is set "1" for longer time than the
sequencer's access cycle using I2C0 from SEQ_CTRL, the
bit of EXE_ERR_STT will become "1".
When the CPU directly accesses SPI, "1" is set on this bit.
SEQ_CTRL holds the access to SPI while the bit is "1".
RW 0x0 Note that if this bit is set "1" for longer time than the
sequencer's access cycle using SPI from SEQ_CTRL, the bit
of EXE_ERR_STT will become "1".
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CXD5602 User Manual