Hitachi AP1 Data Book page 105

------------------------------------------------------HMCS46C,HMCS46CL
These currents and added to the Stand·
by Supply Current (or Halt Current).
.. Disable"1outp.ut ....... NMOS Output: OFF
CMOS Output:
High Impedance
(NMOS, PMOS:
OFF)
Pull up MOS ... OFF
Input ......... Input Circuit: OFF
Both input and output are at high
impedance state. Since an input circuit
is OFF, any current other than the Stand·
by Supply Current (or Halt Current) does
not flow even if an input signal changes.
When the
m::T
pin is set to "I" ("High" level), the HMCS46C
gets into operation from the status just before the Halt State.
The halt timing is shown in Figure 24.
CAUTION
If, during the Halt State, the external reset input is applied
(RESET
=
"I" ("High" level», the internal status is not held.
• OSCILLATOR
The HMCS46C contains its own oscillator and frequency
divider (CPG). The user can obtain the desired timing for opera.
tion of the LSI by merely connecting an resistor Rf or ceramic
filter circuit (Internal Clock Operation). Also an external oscil·
lator can supply a clock (External Clock Operation).
The OSC
I
clock frequency is internally divided by four to
produce the internal system clocks.
The user may exchange the external parts for the same LSI
to select either of these two operational modes as shown in
Figure 25. There is no need of specifying it by using the mask
option.
The typical value of clock oscillation frequency (fose) varies
with a oscillation resistor Rf as shown in Figure 26.
I - - - - - - - - - - - - H a l t S t a t e - - - - - - - - - - - - - . ,
vcc--------~~----------~
HL
T'-------
tfHLT trHLT
OPR
Figure 24 Halt Timing
(a) Internal Clock Operation Using Resistor R
f
Wiring of OSC. and OSC
2
terminals should
R
be
81
short
81
possible because the oscillation
c(
SC.
f frequency Is modified by capacitance of
OSC
2
these terminals.
(b) Internal Clock Operation Using Ceramic Filter Circuit (This is not applied to HMCS46CL.)
c.
~~:~iC~~~~'-~
}C
2
Ceramic Filter; CSB800A (MURATA)
R. 1MO
±
10%
C. 100pF
±
10% (Ceramic Capacitor)
C
2
100pF
±
10% (Ceramic Capacitor)
GND
The ceramic filter oscillation does not apply when using "Halt" and not
resetting at the time of "Halt" cancallation.
Thil circuit il the exemple of the typical u •. AI the oscillation character·
istics il not guaranteed. plea. consider and examine the circuit constants
carefully on your application.
Figure 25 Clock Operation Modes (to be continued)
103